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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Computer Operating Properly - Control registers
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// XGATE Coprocessor - Control registers
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//
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//
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// Author: Bob Hayes
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// Author: Bob Hayes
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// rehayes@opencores.org
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// rehayes@opencores.org
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//
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//
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// Downloaded from: http://www.opencores.org/projects/xgate.....
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// Downloaded from: http://www.opencores.org/projects/xgate.....
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output reg clear_xgif_3, // Strobe for decode to clear interrupt flag bank 3
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output reg clear_xgif_3, // Strobe for decode to clear interrupt flag bank 3
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output reg clear_xgif_2, // Strobe for decode to clear interrupt flag bank 2
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output reg clear_xgif_2, // Strobe for decode to clear interrupt flag bank 2
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output reg clear_xgif_1, // Strobe for decode to clear interrupt flag bank 1
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output reg clear_xgif_1, // Strobe for decode to clear interrupt flag bank 1
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output reg clear_xgif_0, // Strobe for decode to clear interrupt flag bank 0
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output reg clear_xgif_0, // Strobe for decode to clear interrupt flag bank 0
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output reg [15:0] clear_xgif_data, // Data for decode to clear interrupt flag
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output reg [15:0] clear_xgif_data, // Data for decode to clear interrupt flag
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output semaph_stat, // Return Status of Semaphore bit
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output reg brk_irq_ena, // Enable BRK instruction to generate interrupt
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output reg brk_irq_ena, // Enable BRK instruction to generate interrupt
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output [MAX_CHANNEL:1] chan_bypass, // XGATE Interrupt enable or bypass
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output [MAX_CHANNEL:1] chan_bypass, // XGATE Interrupt enable or bypass
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output reg [127:1] irq_bypass, // Register to hold irq bypass control state
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output reg [MAX_CHANNEL:1] irq_bypass, // Register to hold irq bypass control state
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input bus_clk, // Control register bus clock
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input bus_clk, // Control register bus clock
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input async_rst_b, // Async reset signal
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input async_rst_b, // Async reset signal
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input sync_reset, // Syncronous reset signal
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input sync_reset, // Syncronous reset signal
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input [15:0] write_bus, // Write Data Bus
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input [15:0] write_bus, // Write Data Bus
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integer j; // Loop counter for channel bypass counter assigments
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integer j; // Loop counter for channel bypass counter assigments
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integer k; // Loop counter for channel bypass counter assigments
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integer k; // Loop counter for channel bypass counter assigments
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// registers
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// registers
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reg [127:1] irq_bypass_d; // Pseudo regester for routing address and data to irq bypass register
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reg [MAX_CHANNEL:1] irq_bypass_d; // Pseudo regester for routing address and data to irq bypass register
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// Wires
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// Wires
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wire [ 1:0] write_any_xgif;
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wire [ 1:0] write_any_xgif;
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//
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//
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// Channel Bypass Registers
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// Channel Bypass Registers
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// Synthesys should eliminate bits that with D input tied to zero
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// Synthesys should eliminate bits that with D input tied to zero
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always @(posedge bus_clk or negedge async_rst_b)
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always @(posedge bus_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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irq_bypass <= {127{1'b1}};
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irq_bypass <= {MAX_CHANNEL{1'b1}};
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else if (sync_reset)
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else if (sync_reset)
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irq_bypass <= {127{1'b1}};
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irq_bypass <= {MAX_CHANNEL{1'b1}};
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else
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else
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irq_bypass <= irq_bypass_d;
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irq_bypass <= irq_bypass_d;
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// Alias the register name to the output pin name so only the used bit are carried out
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// Alias the register name to the output pin name so only the used bit are carried out
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assign chan_bypass = irq_bypass[MAX_CHANNEL:1];
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assign chan_bypass = irq_bypass[MAX_CHANNEL:1];
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