| Line 67... |
Line 67... |
input risc_clk,
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input risc_clk,
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input async_rst_b,
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input async_rst_b,
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input mem_req_ack, // Memory Bus available - data good
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input mem_req_ack, // Memory Bus available - data good
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input xge, // XGATE Module Enable
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input xge, // XGATE Module Enable
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input xgfrz, // Stop XGATE in Freeze Mode
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input xgfrz, // Stop XGATE in Freeze Mode
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input xgdbg, // XGATE Debug Mode
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input xgdbg_set, // Enter XGATE Debug Mode
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input xgdbg_clear, // Leave XGATE Debug Mode
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input xgss, // XGATE Single Step
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input xgss, // XGATE Single Step
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input [15:1] xgvbr, // XGATE vector Base Address Register
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input [15:1] xgvbr, // XGATE vector Base Address Register
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input [ 6:0] int_req, // Encoded interrupt request
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input [ 6:0] int_req, // Encoded interrupt request
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input xgie, // XGATE Interrupt Enable
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input xgie, // XGATE Interrupt Enable
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input brk_irq_ena, // Enable BRK instruction to generate interrupt
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input brk_irq_ena, // Enable BRK instruction to generate interrupt
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| Line 186... |
Line 187... |
wire perif_wrt_ena; // Enable for Salve writes to CPU registers
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wire perif_wrt_ena; // Enable for Salve writes to CPU registers
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reg xgss_edge; // Flop for edge detection
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reg xgss_edge; // Flop for edge detection
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wire single_step; // Pulse to trigger a single instruction execution in debug mode
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wire single_step; // Pulse to trigger a single instruction execution in debug mode
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reg brk_set_dbg; // Pulse to set debug_active from instruction decoder
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reg brk_set_dbg; // Pulse to set debug_active from instruction decoder
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reg xgdbg_dly; //
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reg cmd_change_pc; // Debug write to PC register
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wire xgdbg_negedge; //
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assign xgate_address = data_access ? data_address : program_counter;
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assign xgate_address = data_access ? data_address : program_counter;
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// Generate an address for an op code fetch from an odd address or a word Load/Store from/to an odd address.
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// Generate an address for an op code fetch from an odd address or a word Load/Store from/to an odd address.
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| Line 202... |
Line 202... |
assign write_mem_data = (write_mem_strb_l || write_mem_strb_h) ? rd_data : 16'b0;
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assign write_mem_data = (write_mem_strb_l || write_mem_strb_h) ? rd_data : 16'b0;
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assign start_thread = xge && (|int_req);
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assign start_thread = xge && (|int_req);
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assign cpu_is_idle = (cpu_state == IDLE);
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assign cpu_is_idle = (cpu_state == IDLE);
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assign perif_wrt_ena = (cpu_is_idle && ~xge) || xgdbg;
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assign perif_wrt_ena = (cpu_is_idle && ~xge) || debug_active;
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// Decode register select for RD and RS
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// Decode register select for RD and RS
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always @*
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always @*
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begin
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begin
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case (op_code[10:8])
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case (op_code[10:8])
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| Line 224... |
Line 224... |
assign wrt_reg_sel = sel_rd_field ? op_code[10:8] : op_code[4:2];
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assign wrt_reg_sel = sel_rd_field ? op_code[10:8] : op_code[4:2];
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// Decode register write select for eather RD or RI/RS2
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// Decode register write select for eather RD or RI/RS2
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always @*
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always @*
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begin
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begin
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wrt_sel_xgr1 = (cpu_state == BOOT_2);
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wrt_sel_xgr1 = (cpu_state == BOOT_3);
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wrt_sel_xgr2 = 1'b0;
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wrt_sel_xgr2 = 1'b0;
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wrt_sel_xgr3 = 1'b0;
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wrt_sel_xgr3 = 1'b0;
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wrt_sel_xgr4 = 1'b0;
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wrt_sel_xgr4 = 1'b0;
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wrt_sel_xgr5 = 1'b0;
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wrt_sel_xgr5 = 1'b0;
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wrt_sel_xgr6 = 1'b0;
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wrt_sel_xgr6 = 1'b0;
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| Line 292... |
Line 292... |
software_error <= addr_error || op_code_error ||
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software_error <= addr_error || op_code_error ||
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(brk_set_dbg && brk_irq_ena) || (software_error && !xgsweif_c);
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(brk_set_dbg && brk_irq_ena) || (software_error && !xgsweif_c);
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assign xg_sw_irq = software_error && xgie;
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assign xg_sw_irq = software_error && xgie;
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// Edge detect xgdbg
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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xgdbg_dly <= 1'b0;
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else
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xgdbg_dly <= xgdbg;
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assign xgdbg_negedge = !xgdbg && xgdbg_dly;
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// Latch the debug state, set by eather xgdb or BRK instructions
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// Latch the debug state, set by eather xgdb or BRK instructions
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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debug_active <= 1'b0;
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debug_active <= 1'b0;
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else
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else
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debug_active <= !xgdbg_negedge && (xgdbg || brk_set_dbg || op_code_error || debug_active);
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debug_active <= !xgdbg_clear && (xgdbg_set || brk_set_dbg || op_code_error || debug_active);
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// Convert xgss (Single Step Pulse) to a one risc_clk wide pulse
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// Convert xgss (Single Step Pulse) to a one risc_clk wide pulse
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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xgss_edge <= 1'b0;
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xgss_edge <= 1'b0;
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| Line 353... |
Line 344... |
if ( !async_rst_b )
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if ( !async_rst_b )
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program_counter <= 16'h0000;
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program_counter <= 16'h0000;
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else
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else
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program_counter <= (write_xgpc && perif_wrt_ena) ? perif_data : (mem_req_ack ? next_pc : program_counter);
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program_counter <= (write_xgpc && perif_wrt_ena) ? perif_data : (mem_req_ack ? next_pc : program_counter);
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// Debug Change Program Counter Register
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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cmd_change_pc <= 1'b0;
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else
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cmd_change_pc <= write_xgpc && perif_wrt_ena;
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// ALU Flag Bits
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// ALU Flag Bits
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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begin
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begin
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carry_flag <= 1'b0;
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carry_flag <= 1'b0;
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| Line 557... |
Line 555... |
next_pc = program_counter;
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next_pc = program_counter;
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end
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end
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{DEBUG, 16'b????????????????} :
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{DEBUG, 16'b????????????????} :
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begin
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begin
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next_cpu_state = xge ? ((single_step || !debug_active) ? CONT : DEBUG) : IDLE;
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next_cpu_state = xge ? ((single_step || !debug_active) ? CONT : (cmd_change_pc ? LD_INST : DEBUG)) : IDLE;
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load_next_inst = 1'b0;
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load_next_inst = cmd_change_pc;
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next_pc = program_counter;
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next_pc = program_counter;
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end
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end
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// Pause here for program counter change of flow or memory write access
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// Pause here for program counter change of flow or memory write access
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// Load next instruction and increment PC
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// Load next instruction and increment PC
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