| Line 74... |
Line 74... |
input xgss, // XGATE Single Step
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input xgss, // XGATE Single Step
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input [15:1] xgvbr, // XGATE vector Base Address Register
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input [15:1] xgvbr, // XGATE vector Base Address Register
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input [ 6:0] int_req, // Encoded interrupt request
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input [ 6:0] int_req, // Encoded interrupt request
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input xgie, // XGATE Interrupt Enable
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input xgie, // XGATE Interrupt Enable
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input brk_irq_ena, // Enable BRK instruction to generate interrupt
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input brk_irq_ena, // Enable BRK instruction to generate interrupt
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input write_xgchid, // Write Strobe for XGCHID register
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input write_xgsem, // Write Strobe for XGSEM register
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input write_xgsem, // Write Strobe for XGSEM register
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input write_xgccr, // Write Strobe for XGATE Condition Code Register
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input write_xgccr, // Write Strobe for XGATE Condition Code Register
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input write_xgpc, // Write Strobe for XGATE Program Counter
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input write_xgpc, // Write Strobe for XGATE Program Counter
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input write_xgr7, // Write Strobe for XGATE Data Register R7
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input write_xgr7, // Write Strobe for XGATE Data Register R7
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input write_xgr6, // Write Strobe for XGATE Data Register R6
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input write_xgr6, // Write Strobe for XGATE Data Register R6
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| Line 113... |
Line 114... |
BREAK_2 = 4'b0110, // Advance PC after Single Step command
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BREAK_2 = 4'b0110, // Advance PC after Single Step command
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LD_INST = 4'b0111, // Load Instruction in Debug mode
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LD_INST = 4'b0111, // Load Instruction in Debug mode
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DEBUG = 4'b1000, // Stop in this state while waiting for debug commands
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DEBUG = 4'b1000, // Stop in this state while waiting for debug commands
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BOOT_1 = 4'b1001, //
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BOOT_1 = 4'b1001, //
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BOOT_2 = 4'b1010, //
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BOOT_2 = 4'b1010, //
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BOOT_3 = 4'b1011; //
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BOOT_3 = 4'b1011, //
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CHG_CHID = 4'b1100;
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// Semaphore states
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// Semaphore states
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parameter [1:0] NO_LOCK = 2'b00,
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parameter [1:0] NO_LOCK = 2'b00,
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RISC_LOCK = 2'b10,
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RISC_LOCK = 2'b10,
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| Line 179... |
Line 181... |
wire shift_rollover;
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wire shift_rollover;
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reg shift_left;
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reg shift_left;
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reg [ 4:0] shift_ammount;
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reg [ 4:0] shift_ammount;
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reg [15:0] shift_filler;
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reg [15:0] shift_filler;
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wire start_thread;
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wire start_thread; // Signle to pop RISC core out of IDLE State
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wire cpu_is_idle; // Processor is in the IDLE state
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wire cpu_is_idle; // Processor is in the IDLE state
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wire perif_wrt_ena; // Enable for Salve writes to CPU registers
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wire perif_wrt_ena; // Enable for Salve writes to CPU registers
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reg xgss_edge; // Flop for edge detection
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reg xgss_edge; // Flop for edge detection
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wire single_step; // Pulse to trigger a single instruction execution in debug mode
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wire single_step; // Pulse to trigger a single instruction execution in debug mode
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reg brk_set_dbg; // Pulse to set debug_active from instruction decoder
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reg brk_set_dbg; // Pulse to set debug_active from instruction decoder
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reg cmd_change_pc; // Debug write to PC register
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reg cmd_change_pc; // Debug write to PC register
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reg [ 1:0] chid_sm_ns; // Pseudo Register,
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reg [ 1:0] chid_sm; //
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wire chid_goto_idle; //
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// Debug states for change CHID
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parameter [1:0] CHID_IDLE = 2'b00,
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CHID_TEST = 2'b10,
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CHID_WAIT = 2'b11;
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assign xgate_address = data_access ? data_address : program_counter;
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assign xgate_address = data_access ? data_address : program_counter;
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// Generate an address for an op code fetch from an odd address or a word Load/Store from/to an odd address.
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// Generate an address for an op code fetch from an odd address or a word Load/Store from/to an odd address.
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assign addr_error = xgate_address[0] && (load_next_inst || (data_access && data_word_op));
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assign addr_error = xgate_address[0] && (load_next_inst || (data_access && data_word_op));
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assign write_mem_strb_l = data_access && data_write && (data_word_op || !data_address[0]);
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assign write_mem_strb_l = data_access && data_write && (data_word_op || !data_address[0]);
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assign write_mem_strb_h = data_access && data_write && (data_word_op || data_address[0]);
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assign write_mem_strb_h = data_access && data_write && (data_word_op || data_address[0]);
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assign write_mem_data = (write_mem_strb_l || write_mem_strb_h) ? rd_data : 16'b0;
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assign write_mem_data = (write_mem_strb_l || write_mem_strb_h) ? rd_data : 16'b0;
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assign start_thread = xge && (|int_req);
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assign start_thread = xge && (|int_req) && !debug_active;
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assign cpu_is_idle = (cpu_state == IDLE);
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assign cpu_is_idle = (cpu_state == IDLE);
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assign perif_wrt_ena = (cpu_is_idle && ~xge) || debug_active;
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assign perif_wrt_ena = (cpu_is_idle && ~xge) || debug_active;
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// Decode register select for RD and RS
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// Decode register select for RD and RS
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| Line 328... |
Line 339... |
// Active Channel Latch
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// Active Channel Latch
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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xgchid <= 7'b0;
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xgchid <= 7'b0;
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else
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else
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xgchid <= (cpu_is_idle && mem_req_ack) ? int_req : xgchid;
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xgchid <= (write_xgchid && debug_active) ? perif_data[6:0] : ((cpu_is_idle && mem_req_ack) ? int_req : xgchid);
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// Channel Change Debug state machine register
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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chid_sm <= CHID_IDLE;
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else
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chid_sm <= chid_sm_ns;
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// Channel Change Debug next state
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always @*
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case (chid_sm)
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CHID_IDLE:
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if ( write_xgchid && debug_active )
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chid_sm_ns = CHID_TEST;
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CHID_TEST:
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if ( !((cpu_state == IDLE) || (cpu_state == CHG_CHID)) && (|xgchid) )
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chid_sm_ns = CHID_IDLE;
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else
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chid_sm_ns = CHID_WAIT;
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CHID_WAIT:
|
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if ( (cpu_state == IDLE) || (cpu_state == CHG_CHID) )
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chid_sm_ns = CHID_IDLE;
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else
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chid_sm_ns = CHID_WAIT;
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default : chid_sm_ns = CHID_IDLE;
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endcase
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assign chid_goto_idle = (chid_sm == CHID_WAIT);
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// CPU Read Data Buffer Register
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// CPU Read Data Buffer Register
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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load_data <= 16'h0000;
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load_data <= 16'h0000;
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| Line 497... |
Line 536... |
next_cpu_state = start_thread ? BOOT_1 : IDLE;
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next_cpu_state = start_thread ? BOOT_1 : IDLE;
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next_pc = program_counter;
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next_pc = program_counter;
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load_next_inst = 1'b0;
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load_next_inst = 1'b0;
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end
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end
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{CHG_CHID, 16'b????????????????} :
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begin
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if (!xge)
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next_cpu_state = IDLE;
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else if (single_step || !debug_active)
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next_cpu_state = BOOT_1;
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else
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next_cpu_state = CHG_CHID;
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next_pc = program_counter;
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load_next_inst = 1'b0;
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end
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// Output RAM address for Program Counter
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// Output RAM address for Program Counter
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{BOOT_1, 16'b????????????????} :
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{BOOT_1, 16'b????????????????} :
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begin
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begin
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next_cpu_state = BOOT_2;
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next_cpu_state = BOOT_2;
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next_pc = program_counter;
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next_pc = program_counter;
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| Line 534... |
Line 586... |
alu_result = load_data;
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alu_result = load_data;
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end
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end
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{BREAK, 16'b????????????????} :
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{BREAK, 16'b????????????????} :
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begin
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begin
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next_cpu_state = xge ? ((single_step || !debug_active) ? BREAK_2 : BREAK) : IDLE;
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if (!xge)
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next_cpu_state = IDLE;
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else if (single_step || !debug_active)
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next_cpu_state = BREAK_2;
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else if (chid_goto_idle)
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next_cpu_state = CHG_CHID;
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else
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next_cpu_state = BREAK;
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// next_cpu_state = (xge && !chid_goto_idle) ?
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// ((single_step || !debug_active) ?
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// BREAK_2 : BREAK) : IDLE;
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load_next_inst = 1'b0;
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load_next_inst = 1'b0;
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next_pc = program_counter;
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next_pc = program_counter;
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end
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end
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{BREAK_2, 16'b????????????????} :
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{BREAK_2, 16'b????????????????} :
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| Line 555... |
Line 617... |
next_pc = program_counter;
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next_pc = program_counter;
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end
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end
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{DEBUG, 16'b????????????????} :
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{DEBUG, 16'b????????????????} :
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begin
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begin
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next_cpu_state = xge ? ((single_step || !debug_active) ? CONT : (cmd_change_pc ? LD_INST : DEBUG)) : IDLE;
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if (!xge)
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next_cpu_state = IDLE;
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else if (single_step || !debug_active)
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next_cpu_state = CONT;
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else if (cmd_change_pc)
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next_cpu_state = LD_INST;
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else if (chid_goto_idle)
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next_cpu_state = CHG_CHID;
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else
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next_cpu_state = DEBUG;
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// next_cpu_state = (xge && !chid_goto_idle) ?
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// ((single_step || !debug_active) ?
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// CONT : (cmd_change_pc ? LD_INST : DEBUG)) : IDLE;
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load_next_inst = cmd_change_pc;
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load_next_inst = cmd_change_pc;
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next_pc = program_counter;
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next_pc = program_counter;
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end
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end
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// Pause here for program counter change of flow or memory write access
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// Pause here for program counter change of flow or memory write access
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