| Line 97... |
Line 97... |
input clear_xgif_1, // Strobe for decode to clear interrupt flag bank 1
|
input clear_xgif_1, // Strobe for decode to clear interrupt flag bank 1
|
input clear_xgif_0, // Strobe for decode to clear interrupt flag bank 0
|
input clear_xgif_0, // Strobe for decode to clear interrupt flag bank 0
|
input [15:0] clear_xgif_data // Data for decode to clear interrupt flag
|
input [15:0] clear_xgif_data // Data for decode to clear interrupt flag
|
);
|
);
|
|
|
integer i, j; // Loop counters for decode of XGATE Interrupt Register
|
integer j; // Loop counters for decode of XGATE Interrupt Register
|
integer k; // Loop counter for Bit Field Insert decode
|
integer k; // Loop counter for Bit Field Insert decode
|
integer bfi, bfii, bfix; // Loop counter for Bit Field Insert function
|
integer bfi, bfii; // Loop counter for Bit Field Insert function
|
|
|
// State machine sequence
|
// State machine sequence
|
parameter [3:0] //synopsys enum state_info
|
parameter [3:0] //synopsys enum state_info
|
IDLE = 4'b0000, // waiting for interrupt
|
IDLE = 4'b0000, // waiting for interrupt
|
CONT = 4'b0001, // Instruction processing state, first state
|
CONT = 4'b0001, // Instruction processing state, first state
|
| Line 218... |
Line 218... |
assign perif_wrt_ena = (cpu_is_idle && ~xge) || debug_active;
|
assign perif_wrt_ena = (cpu_is_idle && ~xge) || debug_active;
|
|
|
// Decode register select for RD and RS
|
// Decode register select for RD and RS
|
always @*
|
always @*
|
begin
|
begin
|
case (op_code[10:8])
|
case (op_code[10:8]) // synopsys parallel_case
|
3'b001 : rd_data = xgr1;
|
3'b001 : rd_data = xgr1;
|
3'b010 : rd_data = xgr2;
|
3'b010 : rd_data = xgr2;
|
3'b011 : rd_data = xgr3;
|
3'b011 : rd_data = xgr3;
|
3'b100 : rd_data = xgr4;
|
3'b100 : rd_data = xgr4;
|
3'b101 : rd_data = xgr5;
|
3'b101 : rd_data = xgr5;
|
| Line 242... |
Line 242... |
wrt_sel_xgr3 = 1'b0;
|
wrt_sel_xgr3 = 1'b0;
|
wrt_sel_xgr4 = 1'b0;
|
wrt_sel_xgr4 = 1'b0;
|
wrt_sel_xgr5 = 1'b0;
|
wrt_sel_xgr5 = 1'b0;
|
wrt_sel_xgr6 = 1'b0;
|
wrt_sel_xgr6 = 1'b0;
|
wrt_sel_xgr7 = 1'b0;
|
wrt_sel_xgr7 = 1'b0;
|
case (wrt_reg_sel)
|
case (wrt_reg_sel) // synopsys parallel_case
|
3'b001 : wrt_sel_xgr1 = mem_req_ack;
|
3'b001 : wrt_sel_xgr1 = mem_req_ack;
|
3'b010 : wrt_sel_xgr2 = mem_req_ack;
|
3'b010 : wrt_sel_xgr2 = mem_req_ack;
|
3'b011 : wrt_sel_xgr3 = mem_req_ack;
|
3'b011 : wrt_sel_xgr3 = mem_req_ack;
|
3'b100 : wrt_sel_xgr4 = mem_req_ack;
|
3'b100 : wrt_sel_xgr4 = mem_req_ack;
|
3'b101 : wrt_sel_xgr5 = mem_req_ack;
|
3'b101 : wrt_sel_xgr5 = mem_req_ack;
|
| Line 255... |
Line 255... |
endcase
|
endcase
|
end
|
end
|
|
|
// Decode register select for RS1 and RB
|
// Decode register select for RS1 and RB
|
always @*
|
always @*
|
case (op_code[7:5])
|
case (op_code[7:5]) // synopsys parallel_case
|
3'b001 : rs1_data = xgr1;
|
3'b001 : rs1_data = xgr1;
|
3'b010 : rs1_data = xgr2;
|
3'b010 : rs1_data = xgr2;
|
3'b011 : rs1_data = xgr3;
|
3'b011 : rs1_data = xgr3;
|
3'b100 : rs1_data = xgr4;
|
3'b100 : rs1_data = xgr4;
|
3'b101 : rs1_data = xgr5;
|
3'b101 : rs1_data = xgr5;
|
| Line 268... |
Line 268... |
default : rs1_data = 16'h0; // XGR0 is always Zero
|
default : rs1_data = 16'h0; // XGR0 is always Zero
|
endcase
|
endcase
|
|
|
// Decode register select for RS2 and RI
|
// Decode register select for RS2 and RI
|
always @*
|
always @*
|
case (op_code[4:2])
|
case (op_code[4:2]) // synopsys parallel_case
|
3'b001 : rs2_data = xgr1;
|
3'b001 : rs2_data = xgr1;
|
3'b010 : rs2_data = xgr2;
|
3'b010 : rs2_data = xgr2;
|
3'b011 : rs2_data = xgr3;
|
3'b011 : rs2_data = xgr3;
|
3'b100 : rs2_data = xgr4;
|
3'b100 : rs2_data = xgr4;
|
3'b101 : rs2_data = xgr5;
|
3'b101 : rs2_data = xgr5;
|
| Line 350... |
Line 350... |
else
|
else
|
chid_sm <= chid_sm_ns;
|
chid_sm <= chid_sm_ns;
|
|
|
// Channel Change Debug next state
|
// Channel Change Debug next state
|
always @*
|
always @*
|
case (chid_sm)
|
case (chid_sm) // synopsys parallel_case
|
CHID_IDLE:
|
CHID_IDLE:
|
if ( write_xgchid && debug_active )
|
if ( write_xgchid && debug_active )
|
chid_sm_ns = CHID_TEST;
|
chid_sm_ns = CHID_TEST;
|
CHID_TEST:
|
CHID_TEST:
|
if ( !((cpu_state == IDLE) || (cpu_state == CHG_CHID)) && (|xgchid) )
|
if ( !((cpu_state == IDLE) || (cpu_state == CHG_CHID)) && (|xgchid) )
|
| Line 850... |
Line 850... |
{CONT, 16'b00001??????10000} :
|
{CONT, 16'b00001??????10000} :
|
begin
|
begin
|
ena_rd_low_byte = 1'b1;
|
ena_rd_low_byte = 1'b1;
|
ena_rd_high_byte = 1'b1;
|
ena_rd_high_byte = 1'b1;
|
|
|
casez (rs1_data)
|
casez (rs1_data) // synopsys parallel_case
|
16'b1???_????_????_???? : alu_result = 16'h000f;
|
16'b1???_????_????_???? : alu_result = 16'h000f;
|
16'b01??_????_????_???? : alu_result = 16'h000e;
|
16'b01??_????_????_???? : alu_result = 16'h000e;
|
16'b001?_????_????_???? : alu_result = 16'h000d;
|
16'b001?_????_????_???? : alu_result = 16'h000d;
|
16'b0001_????_????_???? : alu_result = 16'h000c;
|
16'b0001_????_????_???? : alu_result = 16'h000c;
|
16'b0000_1???_????_???? : alu_result = 16'h000b;
|
16'b0000_1???_????_???? : alu_result = 16'h000b;
|
| Line 1813... |
Line 1813... |
ena_rd_high_byte = 1'b1;
|
ena_rd_high_byte = 1'b1;
|
shift_left = 1'b1;
|
shift_left = 1'b1;
|
shift_ammount = {1'b0, rs2_data[3:0]};
|
shift_ammount = {1'b0, rs2_data[3:0]};
|
shift_in = rs1_data;
|
shift_in = rs1_data;
|
|
|
for (bfi = 0; bfi <= 15; bfi = bfi + 1)
|
for (bfii = 0; bfii <= 15; bfii = bfii + 1)
|
alu_result[bfi] = bf_mux_mask[bfi] ? !(shift_out[bfi] ^ rd_data[bfi]) : rd_data[bfi];
|
alu_result[bfii] = bf_mux_mask[bfii] ? !(shift_out[bfii] ^ rd_data[bfii]) : rd_data[bfii];
|
next_zero = !(|alu_result);
|
next_zero = !(|alu_result);
|
next_negative = alu_result[15];
|
next_negative = alu_result[15];
|
next_overflow = 1'b0;
|
next_overflow = 1'b0;
|
end
|
end
|
|
|
| Line 2040... |
Line 2040... |
|
|
alu_result = {op_code[7:0], 8'b0};
|
alu_result = {op_code[7:0], 8'b0};
|
end
|
end
|
default :
|
default :
|
begin
|
begin
|
|
// synopsys translate_off
|
$display("\nOP Code Error\n");
|
$display("\nOP Code Error\n");
|
|
// synopsys translate_on
|
next_cpu_state = DEBUG;
|
next_cpu_state = DEBUG;
|
next_pc = program_counter;
|
next_pc = program_counter;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
op_code_error = 1'b1;
|
op_code_error = 1'b1;
|
end
|
end
|
| Line 2062... |
Line 2064... |
.shift_filler( shift_filler )
|
.shift_filler( shift_filler )
|
);
|
);
|
|
|
// Three to Eight line decoder
|
// Three to Eight line decoder
|
always @*
|
always @*
|
case (semaph_risc)
|
case (semaph_risc) // synopsys parallel_case
|
4'h0 : semap_risc_bit = 8'b0000_0001;
|
4'h0 : semap_risc_bit = 8'b0000_0001;
|
4'h1 : semap_risc_bit = 8'b0000_0010;
|
4'h1 : semap_risc_bit = 8'b0000_0010;
|
4'h2 : semap_risc_bit = 8'b0000_0100;
|
4'h2 : semap_risc_bit = 8'b0000_0100;
|
4'h3 : semap_risc_bit = 8'b0000_1000;
|
4'h3 : semap_risc_bit = 8'b0000_1000;
|
4'h4 : semap_risc_bit = 8'b0001_0000;
|
4'h4 : semap_risc_bit = 8'b0001_0000;
|
| Line 2222... |
Line 2224... |
input [15:0] shift_in,
|
input [15:0] shift_in,
|
input [15:0] shift_filler
|
input [15:0] shift_filler
|
);
|
);
|
|
|
always @*
|
always @*
|
casez ({shift_left, shift_ammount})
|
casez ({shift_left, shift_ammount}) // synopsys parallel_case
|
// Start Right Shifts
|
// Start Right Shifts
|
6'b0_0_0000 :
|
6'b0_0_0000 :
|
begin
|
begin
|
shift_out = shift_in;
|
shift_out = shift_in;
|
shift_rollover = 1'b0;
|
shift_rollover = 1'b0;
|
| Line 2451... |
Line 2453... |
end
|
end
|
RISC_LOCK:
|
RISC_LOCK:
|
begin
|
begin
|
if (csem && risc_bit_sel)
|
if (csem && risc_bit_sel)
|
next_semap_state = NO_LOCK;
|
next_semap_state = NO_LOCK;
|
|
else
|
|
next_semap_state = RISC_LOCK;
|
end
|
end
|
HOST_LOCK:
|
HOST_LOCK:
|
begin
|
begin
|
if (host_wrt && host_bit_mask && !host_bit)
|
if (host_wrt && host_bit_mask && !host_bit)
|
next_semap_state = NO_LOCK;
|
next_semap_state = NO_LOCK;
|
|
else
|
|
next_semap_state = HOST_LOCK;
|
end
|
end
|
default:
|
default:
|
next_semap_state = NO_LOCK;
|
next_semap_state = NO_LOCK;
|
endcase
|
endcase
|
end
|
end
|
