| Line 54... |
Line 54... |
output reg zero_flag,
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output reg zero_flag,
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output reg negative_flag,
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output reg negative_flag,
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output reg carry_flag,
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output reg carry_flag,
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output reg overflow_flag,
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output reg overflow_flag,
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output reg [ 6:0] xgchid,
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output reg [ 6:0] xgchid,
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output reg [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag
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output reg [127:0] xgif_status, // XGATE Interrupt Flag
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output xg_sw_irq, // Xgate Software interrupt
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output xg_sw_irq, // Xgate Software interrupt
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output [ 7:0] host_semap, // Semaphore status for host
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output [ 7:0] host_semap, // Semaphore status for host
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output reg debug_active, // Latch to control debug mode in the RISC state machine
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output reg debug_active, // Latch to control debug mode in the RISC state machine
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| Line 67... |
Line 67... |
input risc_clk,
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input risc_clk,
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input async_rst_b,
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input async_rst_b,
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input mem_req_ack, // Memory Bus available - data good
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input mem_req_ack, // Memory Bus available - data good
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input xge, // XGATE Module Enable
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input xge, // XGATE Module Enable
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input xgfrz, // Stop XGATE in Freeze Mode
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input xgfrz, // Stop XGATE in Freeze Mode
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input debug_mode_i, // Force RISC core into debug mode
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input xgdbg_set, // Enter XGATE Debug Mode
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input xgdbg_set, // Enter XGATE Debug Mode
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input xgdbg_clear, // Leave XGATE Debug Mode
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input xgdbg_clear, // Leave XGATE Debug Mode
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input xgss, // XGATE Single Step
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input xgss, // XGATE Single Step
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input [15:1] xgvbr, // XGATE vector Base Address Register
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input [15:1] xgvbr, // XGATE vector Base Address Register
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input [ 6:0] int_req, // Encoded interrupt request
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input [ 6:0] int_req, // Encoded interrupt request
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| Line 172... |
Line 173... |
reg wrt_sel_xgr4; // Pseudo Register,
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reg wrt_sel_xgr4; // Pseudo Register,
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reg wrt_sel_xgr5; // Pseudo Register,
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reg wrt_sel_xgr5; // Pseudo Register,
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reg wrt_sel_xgr6; // Pseudo Register,
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reg wrt_sel_xgr6; // Pseudo Register,
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reg wrt_sel_xgr7; // Pseudo Register,
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reg wrt_sel_xgr7; // Pseudo Register,
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reg [MAX_CHANNEL:0] xgif_d;
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reg [127:0] xgif_d;
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reg [15:0] shift_in;
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reg [15:0] shift_in;
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wire [15:0] shift_out;
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wire [15:0] shift_out;
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wire shift_rollover;
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wire shift_rollover;
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reg shift_left;
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reg shift_left;
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| Line 191... |
Line 192... |
reg xgss_edge; // Flop for edge detection
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reg xgss_edge; // Flop for edge detection
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wire single_step; // Pulse to trigger a single instruction execution in debug mode
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wire single_step; // Pulse to trigger a single instruction execution in debug mode
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reg brk_set_dbg; // Pulse to set debug_active from instruction decoder
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reg brk_set_dbg; // Pulse to set debug_active from instruction decoder
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reg cmd_change_pc; // Debug write to PC register
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reg cmd_change_pc; // Debug write to PC register
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reg [ 1:0] chid_sm_ns; // Pseudo Register,
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reg [ 1:0] chid_sm_ns; // Pseudo Register for State Machine next state logic,
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reg [ 1:0] chid_sm; //
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reg [ 1:0] chid_sm; //
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wire chid_goto_idle; //
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wire chid_goto_idle; //
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// Debug states for change CHID
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// Debug states for change CHID
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parameter [1:0] CHID_IDLE = 2'b00,
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parameter [1:0] CHID_IDLE = 2'b00,
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| Line 410... |
Line 411... |
end
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end
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// Interrupt Flag next value
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// Interrupt Flag next value
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always @*
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always @*
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begin
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begin
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xgif_d = 0;
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j = 0;
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j = 0;
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while (j <= MAX_CHANNEL)
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while (j <= MAX_CHANNEL)
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begin
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begin
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xgif_d[j] = xgif[j] || (set_irq_flag == j);
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xgif_d[j] = xgif_status[j] || (set_irq_flag == j);
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j = j + 1;
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j = j + 1;
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end
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end
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if (clear_xgif_0)
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if (clear_xgif_0)
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xgif_d[15: 0] = ~clear_xgif_data & xgif[15: 0];
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xgif_d[15: 0] = ~clear_xgif_data & xgif_status[15: 0];
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if (clear_xgif_1)
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if (clear_xgif_1)
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xgif_d[31:16] = ~clear_xgif_data & xgif[31:16];
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xgif_d[31:16] = ~clear_xgif_data & xgif_status[31:16];
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if (clear_xgif_2)
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if (clear_xgif_2)
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xgif_d[47:32] = ~clear_xgif_data & xgif[47:32];
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xgif_d[47:32] = ~clear_xgif_data & xgif_status[47:32];
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if (clear_xgif_3)
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if (clear_xgif_3)
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xgif_d[63:48] = ~clear_xgif_data & xgif[63:48];
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xgif_d[63:48] = ~clear_xgif_data & xgif_status[63:48];
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if (clear_xgif_4)
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if (clear_xgif_4)
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xgif_d[79:64] = ~clear_xgif_data & xgif[79:64];
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xgif_d[79:64] = ~clear_xgif_data & xgif_status[79:64];
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if (clear_xgif_5)
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if (clear_xgif_5)
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xgif_d[95:80] = ~clear_xgif_data & xgif[95:80];
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xgif_d[95:80] = ~clear_xgif_data & xgif_status[95:80];
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if (clear_xgif_6)
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if (clear_xgif_6)
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xgif_d[111:96] = ~clear_xgif_data & xgif[111:96];
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xgif_d[111:96] = ~clear_xgif_data & xgif_status[111:96];
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if (clear_xgif_7)
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if (clear_xgif_7)
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xgif_d[127:112] = ~clear_xgif_data & xgif[127:112];
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xgif_d[127:112] = ~clear_xgif_data & xgif_status[127:112];
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end
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end
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// Interrupt Flag Registers
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// Interrupt Flag Registers
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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xgif <= 0;
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xgif_status <= 0;
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else
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else
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xgif <= xgif_d;
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xgif_status <= xgif_d;
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// RISC Data Registers
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// RISC Data Registers
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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