Subversion Repositories xgate

  output reg [15:0] xgr5,

  output reg [15:0] xgr5,

  output reg [15:0] xgr6,

  output reg [15:0] xgr6,

  output reg [15:0] xgr7,

  output reg [15:0] xgr7,

  output     [15:0] xgate_address,

  output     [15:0] xgate_address,

  output     [15:0] write_mem_data,   // Data for Memory write

  output     [15:0] write_mem_data,   // Data for Memory write

  output            write_mem_strb_l, // Strobe for writing low data byte

  output            write_mem_strb_l, // Strobe for writing low data byte

  output            write_mem_strb_h, // Strobe for writing high data bye

  output            write_mem_strb_h, // Strobe for writing high data bye

  output reg                 zero_flag,

  output reg                 zero_flag,

  output reg                 negative_flag,

  output reg                 negative_flag,

  output reg                 carry_flag,

  output reg                 carry_flag,

                  CHID_WAIT = 2'b11;

                  CHID_WAIT = 2'b11;

  assign xgate_address = data_access ? data_address : program_counter;

  assign xgate_address = data_access ? data_address : program_counter;

  // Generate an address for an op code fetch from an odd address or a word Load/Store from/to an odd address.

  // Generate an address for an op code fetch from an odd address or a word Load/Store from/to an odd address.

  assign addr_error = xgate_address[0] && (load_next_inst || (data_access && data_word_op));

  assign addr_error = xgate_address[0] && (load_next_inst || (data_access && data_word_op));

  assign write_mem_strb_l = data_access && data_write && (data_word_op || !data_address[0]);

  assign write_mem_strb_l = data_access && data_write && (data_word_op || !data_address[0]);

  assign write_mem_strb_h = data_access && data_write && (data_word_op ||  data_address[0]);

  assign write_mem_strb_h = data_access && data_write && (data_word_op ||  data_address[0]);