| Line 67... |
Line 67... |
input [15:0] perif_data,
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input [15:0] perif_data,
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input risc_clk,
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input risc_clk,
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input async_rst_b,
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input async_rst_b,
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input mem_req_ack, // Memory Bus available - data good
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input mem_req_ack, // Memory Bus available - data good
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input xge, // XGATE Module Enable
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input xge, // XGATE Module Enable
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input xgfrz, // Stop XGATE in Freeze Mode
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input debug_mode_i, // Force RISC core into debug mode
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input debug_mode_i, // Force RISC core into debug mode
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input xgdbg_set, // Enter XGATE Debug Mode
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input xgdbg_set, // Enter XGATE Debug Mode
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input xgdbg_clear, // Leave XGATE Debug Mode
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input xgdbg_clear, // Leave XGATE Debug Mode
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input xgss, // XGATE Single Step
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input xgss, // XGATE Single Step
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input [15:1] xgvbr, // XGATE vector Base Address Register
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input [15:1] xgvbr, // XGATE vector Base Address Register
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| Line 79... |
Line 78... |
input xgie, // XGATE Interrupt Enable
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input xgie, // XGATE Interrupt Enable
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input brk_irq_ena, // Enable BRK instruction to generate interrupt
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input brk_irq_ena, // Enable BRK instruction to generate interrupt
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input write_xgchid, // Write Strobe for XGCHID register
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input write_xgchid, // Write Strobe for XGCHID register
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input write_xgsem, // Write Strobe for XGSEM register
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input write_xgsem, // Write Strobe for XGSEM register
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input write_xgccr, // Write Strobe for XGATE Condition Code Register
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input write_xgccr, // Write Strobe for XGATE Condition Code Register
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input write_xgpc, // Write Strobe for XGATE Program Counter
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input [ 1:0] write_xgpc, // Write Strobe for XGATE Program Counter
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input write_xgr7, // Write Strobe for XGATE Data Register R7
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input [ 1:0] write_xgr7, // Write Strobe for XGATE Data Register R7
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input write_xgr6, // Write Strobe for XGATE Data Register R6
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input [ 1:0] write_xgr6, // Write Strobe for XGATE Data Register R6
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input write_xgr5, // Write Strobe for XGATE Data Register R5
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input [ 1:0] write_xgr5, // Write Strobe for XGATE Data Register R5
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input write_xgr4, // Write Strobe for XGATE Data Register R4
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input [ 1:0] write_xgr4, // Write Strobe for XGATE Data Register R4
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input write_xgr3, // Write Strobe for XGATE Data Register R3
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input [ 1:0] write_xgr3, // Write Strobe for XGATE Data Register R3
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input write_xgr2, // Write Strobe for XGATE Data Register R2
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input [ 1:0] write_xgr2, // Write Strobe for XGATE Data Register R2
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input write_xgr1, // Write Strobe for XGATE Data Register R1
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input [ 1:0] write_xgr1, // Write Strobe for XGATE Data Register R1
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input xgsweif_c, // Clear Software Flag
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input xgsweif_c, // Clear Software Flag
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input clear_xgif_7, // Strobe for decode to clear interrupt flag bank 7
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input clear_xgif_7, // Strobe for decode to clear interrupt flag bank 7
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input clear_xgif_6, // Strobe for decode to clear interrupt flag bank 6
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input clear_xgif_6, // Strobe for decode to clear interrupt flag bank 6
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input clear_xgif_5, // Strobe for decode to clear interrupt flag bank 5
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input clear_xgif_5, // Strobe for decode to clear interrupt flag bank 5
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input clear_xgif_4, // Strobe for decode to clear interrupt flag bank 4
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input clear_xgif_4, // Strobe for decode to clear interrupt flag bank 4
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| Line 393... |
Line 392... |
// Program Counter Register
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// Program Counter Register
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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program_counter <= 16'h0000;
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program_counter <= 16'h0000;
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else
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else
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program_counter <= (write_xgpc && perif_wrt_ena) ? perif_data : (mem_req_ack ? next_pc : program_counter);
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program_counter <= (|write_xgpc && perif_wrt_ena) ?
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{(write_xgpc[1] ? perif_data[15:8]: program_counter[15:8]),
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(write_xgpc[0] ? perif_data[ 7:0]: program_counter[ 7:0])} :
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(mem_req_ack ? next_pc : program_counter);
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// Debug Change Program Counter Register
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// Debug Change Program Counter Register
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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cmd_change_pc <= 1'b0;
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cmd_change_pc <= 1'b0;
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else
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else
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cmd_change_pc <= write_xgpc && perif_wrt_ena;
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cmd_change_pc <= |write_xgpc && perif_wrt_ena;
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// ALU Flag Bits
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// ALU Flag Bits
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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begin
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begin
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| Line 469... |
Line 471... |
xgr6 <= 16'b0;
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xgr6 <= 16'b0;
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xgr7 <= 16'b0;
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xgr7 <= 16'b0;
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end
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end
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else
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else
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begin
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begin
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xgr1 <= (write_xgr1 && perif_wrt_ena) ? perif_data :
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xgr1 <= (|write_xgr1 && perif_wrt_ena) ?
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{(write_xgr1[1] ? perif_data[15:8]: xgr1[15:8]),
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(write_xgr1[0] ? perif_data[ 7:0]: xgr1[ 7:0])} :
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{((wrt_sel_xgr1 && ena_rd_high_byte) ? alu_result[15:8] : xgr1[15:8]),
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{((wrt_sel_xgr1 && ena_rd_high_byte) ? alu_result[15:8] : xgr1[15:8]),
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((wrt_sel_xgr1 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr1[ 7:0])};
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((wrt_sel_xgr1 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr1[ 7:0])};
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xgr2 <= (write_xgr2 && perif_wrt_ena) ? perif_data :
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xgr2 <= (|write_xgr2 && perif_wrt_ena) ?
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{(write_xgr2[1] ? perif_data[15:8]: xgr2[15:8]),
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(write_xgr2[0] ? perif_data[ 7:0]: xgr2[ 7:0])} :
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{((wrt_sel_xgr2 && ena_rd_high_byte) ? alu_result[15:8] : xgr2[15:8]),
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{((wrt_sel_xgr2 && ena_rd_high_byte) ? alu_result[15:8] : xgr2[15:8]),
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((wrt_sel_xgr2 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr2[ 7:0])};
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((wrt_sel_xgr2 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr2[ 7:0])};
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xgr3 <= (write_xgr3 && perif_wrt_ena) ? perif_data :
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xgr3 <= (|write_xgr3 && perif_wrt_ena) ?
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{(write_xgr3[1] ? perif_data[15:8]: xgr3[15:8]),
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(write_xgr3[0] ? perif_data[ 7:0]: xgr3[ 7:0])} :
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{((wrt_sel_xgr3 && ena_rd_high_byte) ? alu_result[15:8] : xgr3[15:8]),
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{((wrt_sel_xgr3 && ena_rd_high_byte) ? alu_result[15:8] : xgr3[15:8]),
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((wrt_sel_xgr3 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr3[ 7:0])};
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((wrt_sel_xgr3 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr3[ 7:0])};
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xgr4 <= (write_xgr4 && perif_wrt_ena) ? perif_data :
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xgr4 <= (|write_xgr4 && perif_wrt_ena) ?
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{(write_xgr4[1] ? perif_data[15:8]: xgr4[15:8]),
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(write_xgr4[0] ? perif_data[ 7:0]: xgr4[ 7:0])} :
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{((wrt_sel_xgr4 && ena_rd_high_byte) ? alu_result[15:8] : xgr4[15:8]),
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{((wrt_sel_xgr4 && ena_rd_high_byte) ? alu_result[15:8] : xgr4[15:8]),
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((wrt_sel_xgr4 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr4[ 7:0])};
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((wrt_sel_xgr4 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr4[ 7:0])};
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xgr5 <= (write_xgr5 && perif_wrt_ena) ? perif_data :
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xgr5 <= (|write_xgr5 && perif_wrt_ena) ?
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{(write_xgr5[1] ? perif_data[15:8]: xgr5[15:8]),
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(write_xgr5[0] ? perif_data[ 7:0]: xgr5[ 7:0])} :
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{((wrt_sel_xgr5 && ena_rd_high_byte) ? alu_result[15:8] : xgr5[15:8]),
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{((wrt_sel_xgr5 && ena_rd_high_byte) ? alu_result[15:8] : xgr5[15:8]),
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((wrt_sel_xgr5 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr5[ 7:0])};
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((wrt_sel_xgr5 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr5[ 7:0])};
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xgr6 <= (write_xgr6 && perif_wrt_ena) ? perif_data :
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xgr6 <= (|write_xgr6 && perif_wrt_ena) ?
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{(write_xgr6[1] ? perif_data[15:8]: xgr6[15:8]),
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(write_xgr6[0] ? perif_data[ 7:0]: xgr6[ 7:0])} :
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{((wrt_sel_xgr6 && ena_rd_high_byte) ? alu_result[15:8] : xgr6[15:8]),
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{((wrt_sel_xgr6 && ena_rd_high_byte) ? alu_result[15:8] : xgr6[15:8]),
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((wrt_sel_xgr6 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr6[ 7:0])};
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((wrt_sel_xgr6 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr6[ 7:0])};
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xgr7 <= (write_xgr7 && perif_wrt_ena) ? perif_data :
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xgr7 <= (|write_xgr7 && perif_wrt_ena) ?
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{(write_xgr7[1] ? perif_data[15:8]: xgr7[15:8]),
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(write_xgr7[0] ? perif_data[ 7:0]: xgr7[ 7:0])} :
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{((wrt_sel_xgr7 && ena_rd_high_byte) ? alu_result[15:8] : xgr7[15:8]),
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{((wrt_sel_xgr7 && ena_rd_high_byte) ? alu_result[15:8] : xgr7[15:8]),
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((wrt_sel_xgr7 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr7[ 7:0])};
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((wrt_sel_xgr7 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr7[ 7:0])};
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end
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end
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// V Ñ Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
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// V Ñ Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
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