| Line 241... |
Line 241... |
3'b111 : rd_data = xgr7;
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3'b111 : rd_data = xgr7;
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default : rd_data = 16'h0; // XGR0 is always Zero
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default : rd_data = 16'h0; // XGR0 is always Zero
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endcase
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endcase
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end
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end
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assign wrt_reg_sel = sel_rd_field ? op_code[10:8] : op_code[4:2];
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assign wrt_reg_sel = (cpu_state == BOOT_3) ? 3'b001 :
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(sel_rd_field ? op_code[10:8] : op_code[4:2]);
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// Decode register write select for eather RD or RI/RS2
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// Decode register write select for eather RD or RI/RS2
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always @*
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always @*
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begin
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begin
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wrt_sel_xgr1 = (cpu_state == BOOT_3);
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wrt_sel_xgr1 = (wrt_reg_sel == 3'b001) && mem_req_ack;
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wrt_sel_xgr2 = 1'b0;
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wrt_sel_xgr2 = (wrt_reg_sel == 3'b010) && mem_req_ack;
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wrt_sel_xgr3 = 1'b0;
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wrt_sel_xgr3 = (wrt_reg_sel == 3'b011) && mem_req_ack;
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wrt_sel_xgr4 = 1'b0;
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wrt_sel_xgr4 = (wrt_reg_sel == 3'b100) && mem_req_ack;
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wrt_sel_xgr5 = 1'b0;
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wrt_sel_xgr5 = (wrt_reg_sel == 3'b101) && mem_req_ack;
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wrt_sel_xgr6 = 1'b0;
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wrt_sel_xgr6 = (wrt_reg_sel == 3'b110) && mem_req_ack;
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wrt_sel_xgr7 = 1'b0;
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wrt_sel_xgr7 = (wrt_reg_sel == 3'b111) && mem_req_ack;
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case (wrt_reg_sel) // synopsys parallel_case
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3'b001 : wrt_sel_xgr1 = mem_req_ack;
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3'b010 : wrt_sel_xgr2 = mem_req_ack;
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3'b011 : wrt_sel_xgr3 = mem_req_ack;
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3'b100 : wrt_sel_xgr4 = mem_req_ack;
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3'b101 : wrt_sel_xgr5 = mem_req_ack;
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3'b110 : wrt_sel_xgr6 = mem_req_ack;
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3'b111 : wrt_sel_xgr7 = mem_req_ack;
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endcase
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end
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end
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|
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// Decode register select for RS1 and RB
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// Decode register select for RS1 and RB
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always @*
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always @*
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case (op_code[7:5]) // synopsys parallel_case
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case (op_code[7:5]) // synopsys parallel_case
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| Line 1240... |
Line 1232... |
begin
|
begin
|
ena_rd_low_byte = 1'b1;
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ena_rd_low_byte = 1'b1;
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ena_rd_high_byte = 1'b1;
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ena_rd_high_byte = 1'b1;
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|
|
{next_carry, alu_result} = rs1_data - rs2_data - {15'b0, carry_flag};
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{next_carry, alu_result} = rs1_data - rs2_data - {15'b0, carry_flag};
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next_zero = !(|alu_result);
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next_zero = !(|alu_result) && zero_flag;
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next_negative = alu_result[15];
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next_negative = alu_result[15];
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next_overflow = (rs1_data[15] && !rs2_data[15] && !alu_result[15]) || (!rs1_data[15] && rs2_data[15] && alu_result[15]);
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next_overflow = (rs1_data[15] && !rs2_data[15] && !alu_result[15]) || (!rs1_data[15] && rs2_data[15] && alu_result[15]);
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end
|
end
|
|
|
// Instruction = ADD RD, RS1, RS2, Op Code = 0 0 0 1 1 RD RS1 RS2 1 0
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// Instruction = ADD RD, RS1, RS2, Op Code = 0 0 0 1 1 RD RS1 RS2 1 0
|
| Line 1270... |
Line 1262... |
begin
|
begin
|
ena_rd_low_byte = 1'b1;
|
ena_rd_low_byte = 1'b1;
|
ena_rd_high_byte = 1'b1;
|
ena_rd_high_byte = 1'b1;
|
|
|
{next_carry, alu_result} = rs1_data + rs2_data + {15'b0, carry_flag};
|
{next_carry, alu_result} = rs1_data + rs2_data + {15'b0, carry_flag};
|
next_zero = !(|alu_result);
|
next_zero = !(|alu_result) && zero_flag;
|
next_negative = alu_result[15];
|
next_negative = alu_result[15];
|
next_overflow = (rs1_data[15] && rs2_data[15] && !alu_result[15]) || (!rs1_data[15] && !rs2_data[15] && alu_result[15]);
|
next_overflow = (rs1_data[15] && rs2_data[15] && !alu_result[15]) || (!rs1_data[15] && !rs2_data[15] && alu_result[15]);
|
end
|
end
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|
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// -----------------------------------------------------------------------
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// -----------------------------------------------------------------------
|
