| Line 59... |
Line 59... |
output reg [ 6:0] xgchid,
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output reg [ 6:0] xgchid,
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output reg [127:0] xgif_status, // XGATE Interrupt Flag
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output reg [127:0] xgif_status, // XGATE Interrupt Flag
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output xg_sw_irq, // Xgate Software interrupt
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output xg_sw_irq, // Xgate Software interrupt
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output [ 7:0] host_semap, // Semaphore status for host
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output [ 7:0] host_semap, // Semaphore status for host
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output reg debug_active, // Latch to control debug mode in the RISC state machine
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output reg debug_active, // Latch to control debug mode in the RISC state machine
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output debug_ack, // Clear debug register
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output single_step, // Pulse to trigger a single instruction execution in debug mode
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input [15:0] read_mem_data,
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input [15:0] read_mem_data,
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input [15:0] perif_data,
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input [15:0] perif_data,
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input risc_clk,
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input risc_clk,
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input async_rst_b,
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input async_rst_b,
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input mem_req_ack, // Memory Bus available - data good
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input mem_req_ack, // Memory Bus available - data good
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input ss_mem_ack, // WISHBONE Bus has granted single step memory access
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input xge, // XGATE Module Enable
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input xge, // XGATE Module Enable
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input debug_mode_i, // Force RISC core into debug mode
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input debug_mode_i, // Force RISC core into debug mode
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input xgdbg_set, // Enter XGATE Debug Mode
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input xgdbg_set, // Enter XGATE Debug Mode, pulse
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input xgdbg_clear, // Leave XGATE Debug Mode
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input xgdbg_clear, // Leave XGATE Debug Mode
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input xgss, // XGATE Single Step
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input xgss, // XGATE Single Step
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input [15:1] xgvbr, // XGATE vector Base Address Register
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input [15:1] xgvbr, // XGATE vector Base Address Register
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input [ 6:0] int_req, // Encoded interrupt request
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input [ 6:0] int_req, // Encoded interrupt request
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input xgie, // XGATE Interrupt Enable
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input xgie, // XGATE Interrupt Enable
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| Line 186... |
Line 189... |
wire [15:0] shift_out;
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wire [15:0] shift_out;
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wire shift_rollover;
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wire shift_rollover;
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reg shift_left;
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reg shift_left;
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reg [ 4:0] shift_ammount;
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reg [ 4:0] shift_ammount;
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reg [15:0] shift_filler;
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reg [15:0] shift_filler;
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reg [15:0] bf_mux_mask; // Mask for controlling mux's in Bit Field Insert Instructions
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wire start_thread; // Signle to pop RISC core out of IDLE State
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wire start_thread; // Signle to pop RISC core out of IDLE State
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wire cpu_is_idle; // Processor is in the IDLE state
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wire cpu_is_idle; // Processor is in the IDLE state
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wire perif_wrt_ena; // Enable for Salve writes to CPU registers
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wire perif_wrt_ena; // Enable for Salve writes to CPU registers
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reg xgss_edge; // Flop for edge detection
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reg xgss_edge; // Flop for edge detection
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wire single_step; // Pulse to trigger a single instruction execution in debug mode
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reg brk_set_dbg; // Pulse to set debug_active from instruction decoder
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reg brk_set_dbg; // Pulse to set debug_active from instruction decoder
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reg cmd_change_pc; // Debug write to PC register
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reg cmd_change_pc; // Debug write to PC register
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reg debug_edge; // Reg for edge detection
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reg [ 1:0] chid_sm_ns; // Pseudo Register for State Machine next state logic,
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reg [ 1:0] chid_sm_ns; // Pseudo Register for State Machine next state logic,
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reg [ 1:0] chid_sm; //
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reg [ 1:0] chid_sm; //
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wire chid_goto_idle; //
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wire chid_goto_idle; //
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| Line 212... |
Line 216... |
assign bra_offset = {{5{op_code[9]}}, op_code[9:0], 1'b0};
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assign bra_offset = {{5{op_code[9]}}, op_code[9:0], 1'b0};
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assign pc_sum = program_counter + pc_incr_mux;
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assign pc_sum = program_counter + pc_incr_mux;
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assign xgate_address = data_access ? data_address : program_counter;
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assign xgate_address = data_access ? data_address : program_counter;
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assign mem_access = data_access || load_next_inst;
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//assign mem_access = data_access || load_next_inst || (start_thread);
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assign mem_access = data_access || load_next_inst || (cpu_state == CONT) ||
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(cpu_state == BREAK_2) || (start_thread);
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// Generate an address for an op code fetch from an odd address or a word Load/Store from/to an odd address.
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// Generate an address for an op code fetch from an odd address or a word Load/Store from/to an odd address.
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assign addr_error = xgate_address[0] && (load_next_inst || (data_access && data_word_op));
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assign addr_error = xgate_address[0] && (load_next_inst || (data_access && data_word_op));
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assign write_mem_strb_l = data_access && data_write && (data_word_op || !data_address[0]);
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assign write_mem_strb_l = data_access && data_write && (data_word_op || !data_address[0]);
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| Line 282... |
Line 288... |
3'b110 : rs2_data = xgr6;
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3'b110 : rs2_data = xgr6;
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3'b111 : rs2_data = xgr7;
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3'b111 : rs2_data = xgr7;
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default : rs2_data = 16'h0; // XGR0 is always Zero
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default : rs2_data = 16'h0; // XGR0 is always Zero
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endcase
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endcase
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reg [15:0] bf_mux_mask; // Mask for controlling mux's in Bit Field Insert Instructions
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// Decode mux select mask for Bit Field Insert Instructions
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// Decode mux select mask for Bit Field Insert Instructions
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always @*
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always @*
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begin
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begin
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k = 0;
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k = 0;
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while (k < 16)
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while (k < 16)
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| Line 309... |
Line 314... |
assign xg_sw_irq = software_error && xgie;
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assign xg_sw_irq = software_error && xgie;
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// Latch the debug state, set by eather xgdb or BRK instructions
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// Latch the debug state, set by eather xgdb or BRK instructions
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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begin
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debug_active <= 1'b0;
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debug_active <= 1'b0;
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debug_edge <= 0;
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end
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else
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else
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debug_active <= !xgdbg_clear && (xgdbg_set || brk_set_dbg || op_code_error || debug_active);
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begin
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debug_active <= !xgdbg_clear && ((xgdbg_set && mem_req_ack && (next_cpu_state == CONT)) || brk_set_dbg || op_code_error || debug_active);
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debug_edge <= debug_active;
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end
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assign debug_ack = debug_active && !debug_edge; // Posedge of debug_active
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// Convert xgss (Single Step Pulse) to a one risc_clk wide pulse
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// Convert xgss (Single Step Pulse) to a one risc_clk wide pulse
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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xgss_edge <= 1'b0;
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xgss_edge <= 1'b0;
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else
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else
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xgss_edge <= xgss;
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xgss_edge <= xgss;
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assign single_step = xgss && !xgss_edge;
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assign single_step = (xgss && !xgss_edge) || (!debug_active && debug_edge);
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// CPU State Register
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// CPU State Register
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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cpu_state <= IDLE;
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cpu_state <= IDLE;
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else
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else
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cpu_state <= mem_req_ack ? next_cpu_state : cpu_state;
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cpu_state <= (mem_req_ack || (chid_sm != CHID_IDLE)) ? next_cpu_state : cpu_state;
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// CPU Instruction Register
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// CPU Instruction Register
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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op_code <= 16'h0000;
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op_code <= 16'h0000;
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| Line 394... |
Line 407... |
// Debug Change Program Counter Register
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// Debug Change Program Counter Register
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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cmd_change_pc <= 1'b0;
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cmd_change_pc <= 1'b0;
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else
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else
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cmd_change_pc <= |write_xgpc && perif_wrt_ena;
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cmd_change_pc <= (|write_xgpc && perif_wrt_ena) || (cmd_change_pc && !mem_req_ack);
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// ALU Flag Bits
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// ALU Flag Bits
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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begin
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begin
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| Line 562... |
Line 575... |
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{CHG_CHID, 16'b????????????????} :
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{CHG_CHID, 16'b????????????????} :
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begin
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begin
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if (!xge)
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if (!xge)
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next_cpu_state = IDLE;
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next_cpu_state = IDLE;
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else if (single_step || !debug_active)
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else if (ss_mem_ack || !debug_active)
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next_cpu_state = BOOT_1;
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next_cpu_state = BOOT_1;
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else
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else
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next_cpu_state = CHG_CHID;
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next_cpu_state = CHG_CHID;
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pc_incr_mux = 16'h0000;
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pc_incr_mux = 16'h0000;
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| Line 611... |
Line 624... |
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{BREAK, 16'b????????????????} :
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{BREAK, 16'b????????????????} :
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begin
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begin
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if (!xge)
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if (!xge)
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next_cpu_state = IDLE;
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next_cpu_state = IDLE;
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else if (single_step || !debug_active)
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else if (ss_mem_ack || !debug_active)
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next_cpu_state = BREAK_2;
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next_cpu_state = BREAK_2;
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else if (chid_goto_idle)
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else if (chid_goto_idle)
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next_cpu_state = CHG_CHID;
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next_cpu_state = CHG_CHID;
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else
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else
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next_cpu_state = BREAK;
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next_cpu_state = BREAK;
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| Line 639... |
Line 652... |
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{DEBUG, 16'b????????????????} :
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{DEBUG, 16'b????????????????} :
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begin
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begin
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if (!xge)
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if (!xge)
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next_cpu_state = IDLE;
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next_cpu_state = IDLE;
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else if (single_step || !debug_active)
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else if (ss_mem_ack || !debug_active)
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next_cpu_state = CONT;
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next_cpu_state = CONT;
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else if (cmd_change_pc)
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else if (cmd_change_pc)
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next_cpu_state = LD_INST;
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next_cpu_state = LD_INST;
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else if (chid_goto_idle)
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else if (chid_goto_idle)
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next_cpu_state = CHG_CHID;
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next_cpu_state = CHG_CHID;
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