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                  HOST_LOCK = 2'b11;

                  HOST_LOCK = 2'b11;

  reg  [ 3:0] cpu_state;         // State register for instruction processing

  reg  [ 3:0] cpu_state;         // State register for instruction processing

  reg  [ 3:0] next_cpu_state;    // Pseudo Register,

  reg  [ 3:0] next_cpu_state;    // Pseudo Register,

  reg         load_next_inst;    // Pseudo Register,

  reg         load_next_inst;    // Pseudo Register,

  reg  [15:0] program_counter;   // Program Counter register

  reg  [15:0] program_counter;   // Program Counter register

  wire [15:0] pc_sum;            // Program Counter Adder

  wire [15:0] pc_sum;            // Program Counter Adder

  reg  [15:0] pc_incr_mux;       // Pseudo Register, mux to select the Program Counter Increment value

  reg  [15:0] pc_incr_mux;       // Pseudo Register, mux to select the Program Counter Increment value

  reg  [15:0] next_pc;           // Pseudo Register

  reg  [15:0] next_pc;           // Pseudo Register

  reg         xgss_edge;     // Flop for edge detection

  reg         xgss_edge;     // Flop for edge detection

  reg         brk_set_dbg;   // Pulse to set debug_active from instruction decoder

  reg         brk_set_dbg;   // Pulse to set debug_active from instruction decoder

  reg         cmd_change_pc; // Debug write to PC register

  reg         cmd_change_pc; // Debug write to PC register

  reg         debug_edge;    // Reg for edge detection

  reg         debug_edge;    // Reg for edge detection

  reg  [ 1:0] chid_sm_ns;    // Pseudo Register for State Machine next state logic,

  reg  [ 1:0] chid_sm_ns;    // Pseudo Register for State Machine next state logic,

  reg  [ 1:0] chid_sm;       //

  reg  [ 1:0] chid_sm;       //

  wire        chid_goto_idle; //

  wire        chid_goto_idle; //

  // Debug states for change CHID

  // Debug states for change CHID

  parameter [1:0] CHID_IDLE = 2'b00,

  parameter [1:0] CHID_IDLE = 2'b00,

                  CHID_TEST = 2'b10,

                  CHID_TEST = 2'b10,

                  CHID_WAIT = 2'b11;

                  CHID_WAIT = 2'b11;

  assign jump_offset = {{6{op_code[8]}}, op_code[8:0], 1'b0};

  assign jump_offset = {{6{op_code[8]}}, op_code[8:0], 1'b0};

  assign bra_offset  = {{5{op_code[9]}}, op_code[9:0], 1'b0};

  assign bra_offset  = {{5{op_code[9]}}, op_code[9:0], 1'b0};

  assign pc_sum      = program_counter + pc_incr_mux;

  assign pc_sum      = program_counter + pc_incr_mux;

  assign xgate_address = data_access ? data_address : program_counter;

  assign xgate_address = data_access ? data_address : program_counter;

      software_error <= addr_error || op_code_error ||

      software_error <= addr_error || op_code_error ||

                        (brk_set_dbg && brk_irq_ena) || (software_error && !xgsweif_c);

                        (brk_set_dbg && brk_irq_ena) || (software_error && !xgsweif_c);

  assign xg_sw_irq = software_error && xgie;

  assign xg_sw_irq = software_error && xgie;

  //  Latch the debug state, set by eather xgdb or BRK instructions

  //  Latch the debug state, set by eather xgdb or BRK instructions

  always @(posedge risc_clk or negedge async_rst_b)

  always @(posedge risc_clk or negedge async_rst_b)

    if ( !async_rst_b )

    if ( !async_rst_b )

      begin

      begin

      debug_active  <= 1'b0;

      debug_active  <= 1'b0;

      debug_edge    <= 0;

      debug_edge    <= 0;

      end

      end

    else

    else

      begin

      begin

                       brk_set_dbg || op_code_error || debug_active);

                       brk_set_dbg || op_code_error || debug_active);

      debug_edge    <= debug_active;

      debug_edge    <= debug_active;

      end

      end

  assign debug_ack = debug_active && !debug_edge; // Posedge of debug_active

  assign debug_ack = debug_active && !debug_edge; // Posedge of debug_active

    else

    else

      xgss_edge  <= xgss;

      xgss_edge  <= xgss;

  assign single_step = (xgss && !xgss_edge) || (!debug_active && debug_edge);

  assign single_step = (xgss && !xgss_edge) || (!debug_active && debug_edge);

  assign stm_auto_advance = (chid_sm != CHID_IDLE);

  assign stm_auto_advance = (chid_sm != CHID_IDLE);

  //  CPU State Register

  //  CPU State Register

  always @(posedge risc_clk or negedge async_rst_b)

  always @(posedge risc_clk or negedge async_rst_b)

    if ( !async_rst_b )

    if ( !async_rst_b )

      cpu_state  <= IDLE;

      cpu_state  <= IDLE;

    else

    else

      program_counter  <= (|write_xgpc && perif_wrt_ena) ?

      program_counter  <= (|write_xgpc && perif_wrt_ena) ?

      {(write_xgpc[1] ? perif_data[15:8]: program_counter[15:8]),

      {(write_xgpc[1] ? perif_data[15:8]: program_counter[15:8]),

       (write_xgpc[0] ? perif_data[ 7:0]: program_counter[ 7:0])} :

       (write_xgpc[0] ? perif_data[ 7:0]: program_counter[ 7:0])} :

      (mem_req_ack ? next_pc : program_counter);

      (mem_req_ack ? next_pc : program_counter);

  //  Debug Change Program Counter Register

  //  Debug Change Program Counter Register

  always @(posedge risc_clk or negedge async_rst_b)

  always @(posedge risc_clk or negedge async_rst_b)

    if ( !async_rst_b )

    if ( !async_rst_b )

      cmd_change_pc  <= 1'b0;

      cmd_change_pc  <= 1'b0;

  always @*

  always @*

    begin

    begin

      ena_rd_low_byte  = 1'b0;

      ena_rd_low_byte  = 1'b0;

      ena_rd_high_byte = 1'b0;

      ena_rd_high_byte = 1'b0;

      load_next_inst = 1'b1;

      load_next_inst = 1'b1;

      next_pc        = pc_sum;    // ""

      next_pc        = pc_sum;    // ""

      next_zero      = zero_flag;

      next_zero      = zero_flag;

      next_negative  = negative_flag;

      next_negative  = negative_flag;

      next_carry     = carry_flag;

      next_carry     = carry_flag;