OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_risc.v] - Diff between revs 67 and 72

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 67 Rev 72
Line 55... Line 55...
  output reg                 zero_flag,
  output reg                 zero_flag,
  output reg                 negative_flag,
  output reg                 negative_flag,
  output reg                 carry_flag,
  output reg                 carry_flag,
  output reg                 overflow_flag,
  output reg                 overflow_flag,
  output reg          [ 6:0] xgchid,
  output reg          [ 6:0] xgchid,
  output reg         [127:0] xgif_status,   // XGATE Interrupt Flag
  output reg         [127:1] xgif_status,   // XGATE Interrupt Flag
  output                     xg_sw_irq,     // Xgate Software interrupt
  output                     xg_sw_irq,     // Xgate Software interrupt
  output              [ 7:0] host_semap,    // Semaphore status for host
  output              [ 7:0] host_semap,    // Semaphore status for host
  output reg                 debug_active,  // Latch to control debug mode in the RISC state machine
  output reg                 debug_active,  // Latch to control debug mode in the RISC state machine
  output                     debug_ack,     // Clear debug register
  output                     debug_ack,     // Clear debug register
  output                     single_step,   // Pulse to trigger a single instruction execution in debug mode
  output                     single_step,   // Pulse to trigger a single instruction execution in debug mode
Line 182... Line 182...
  reg         wrt_sel_xgr4;   // Pseudo Register,
  reg         wrt_sel_xgr4;   // Pseudo Register,
  reg         wrt_sel_xgr5;   // Pseudo Register,
  reg         wrt_sel_xgr5;   // Pseudo Register,
  reg         wrt_sel_xgr6;   // Pseudo Register,
  reg         wrt_sel_xgr6;   // Pseudo Register,
  reg         wrt_sel_xgr7;   // Pseudo Register,
  reg         wrt_sel_xgr7;   // Pseudo Register,
 
 
  reg [127:0] xgif_d;
  reg [127:1] xgif_d;
 
 
  reg  [15:0] shift_in;
  reg  [15:0] shift_in;
  wire [15:0] shift_out;
  wire [15:0] shift_out;
  wire        shift_rollover;
  wire        shift_rollover;
  reg         shift_left;
  reg         shift_left;
Line 448... Line 448...
 
 
  //  Interrupt Flag next value
  //  Interrupt Flag next value
  always @*
  always @*
    begin
    begin
      xgif_d = 0;
      xgif_d = 0;
      j = 0;
      j = 1;
      while (j <= MAX_CHANNEL)
      while (j <= MAX_CHANNEL)  // while loop sets irq bit and maintains previously set bits
        begin
        begin
         xgif_d[j]  = xgif_status[j] || (set_irq_flag == j);
         xgif_d[j]  = xgif_status[j] || (set_irq_flag == j);
         j = j + 1;
         j = j + 1;
        end
        end
      if (clear_xgif_0)
      if (clear_xgif_0)
        xgif_d[15: 0]  = ~clear_xgif_data & xgif_status[15: 0];
        xgif_d[15: 1]  = ~clear_xgif_data & xgif_status[15: 1];
      if (clear_xgif_1)
      if (clear_xgif_1)
        xgif_d[31:16]  = ~clear_xgif_data & xgif_status[31:16];
        xgif_d[31:16]  = ~clear_xgif_data & xgif_status[31:16];
      if (clear_xgif_2)
      if (clear_xgif_2)
        xgif_d[47:32]  = ~clear_xgif_data & xgif_status[47:32];
        xgif_d[47:32]  = ~clear_xgif_data & xgif_status[47:32];
      if (clear_xgif_3)
      if (clear_xgif_3)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.