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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_risc.v] - Diff between revs 72 and 75
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| Rev 72 |
Rev 75 |
| Line 388... |
Line 388... |
always @*
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always @*
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case (chid_sm) // synopsys parallel_case
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case (chid_sm) // synopsys parallel_case
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CHID_IDLE:
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CHID_IDLE:
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if ( write_xgchid && debug_active )
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if ( write_xgchid && debug_active )
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chid_sm_ns = CHID_TEST;
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chid_sm_ns = CHID_TEST;
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else
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chid_sm_ns = CHID_IDLE;
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CHID_TEST:
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CHID_TEST:
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if ( !((cpu_state == IDLE) || (cpu_state == CHG_CHID)) && (|xgchid) )
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if ( !((cpu_state == IDLE) || (cpu_state == CHG_CHID)) && (|xgchid) )
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chid_sm_ns = CHID_IDLE;
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chid_sm_ns = CHID_IDLE;
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else
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else
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chid_sm_ns = CHID_WAIT;
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chid_sm_ns = CHID_WAIT;
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| Line 2375... |
Line 2377... |
6'b1_1_???? :
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6'b1_1_???? :
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begin
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begin
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shift_out = shift_filler[15: 0];
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shift_out = shift_filler[15: 0];
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shift_rollover = shift_in[ 0];
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shift_rollover = shift_in[ 0];
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end
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end
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default :
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begin
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shift_out = shift_in;
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shift_rollover = 1'b0;
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end
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endcase
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endcase
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endmodule // xgate_barrel_shift
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endmodule // xgate_barrel_shift
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