| Line 533... |
Line 533... |
(write_xgr7[0] ? perif_data[ 7:0]: xgr7[ 7:0])} :
|
(write_xgr7[0] ? perif_data[ 7:0]: xgr7[ 7:0])} :
|
{((wrt_sel_xgr7 && ena_rd_high_byte) ? alu_result[15:8] : xgr7[15:8]),
|
{((wrt_sel_xgr7 && ena_rd_high_byte) ? alu_result[15:8] : xgr7[15:8]),
|
((wrt_sel_xgr7 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr7[ 7:0])};
|
((wrt_sel_xgr7 && ena_rd_low_byte) ? alu_result[ 7:0] : xgr7[ 7:0])};
|
end
|
end
|
|
|
// V Ñ Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
|
// V - Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
|
// P Ñ Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
|
// P - Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
|
// r Ñ 8-bit data read: lasts for at least one RISC core cycle
|
// r - 8-bit data read: lasts for at least one RISC core cycle
|
// R Ñ 16-bit data read: lasts for at least one RISC core cycle
|
// R - 16-bit data read: lasts for at least one RISC core cycle
|
// w Ñ 8-bit data write: lasts for at least one RISC core cycle
|
// w - 8-bit data write: lasts for at least one RISC core cycle
|
// W Ñ 16-bit data write: lasts for at least one RISC core cycle
|
// W - 16-bit data write: lasts for at least one RISC core cycle
|
// A Ñ Alignment cycle: no read or write, lasts for zero or one RISC core cycles
|
// A - Alignment cycle: no read or write, lasts for zero or one RISC core cycles
|
// f Ñ Free cycle: no read or write, lasts for one RISC core cycles
|
// f - Free cycle: no read or write, lasts for one RISC core cycles
|
// Special Cases
|
// Special Cases
|
// PP/P Ñ Branch: PP if branch taken, P if not taken
|
// PP/P - Branch: PP if branch taken, P if not taken
|
|
|
always @*
|
always @*
|
begin
|
begin
|
ena_rd_low_byte = 1'b0;
|
ena_rd_low_byte = 1'b0;
|
ena_rd_high_byte = 1'b0;
|
ena_rd_high_byte = 1'b0;
|
| Line 848... |
Line 848... |
// Instruction = SIF RS, Op Code = 0 0 0 0 0 RS 1 1 1 1 0 1 1 1
|
// Instruction = SIF RS, Op Code = 0 0 0 0 0 RS 1 1 1 1 0 1 1 1
|
// Sets the Interrupt Flag associated with the channel id number
|
// Sets the Interrupt Flag associated with the channel id number
|
// contained in RS[6:0] is set. The content of RS[15:7] is ignored
|
// contained in RS[6:0] is set. The content of RS[15:7] is ignored
|
// Cycles - P
|
// Cycles - P
|
{CONT, 16'b00000???11110111} :
|
{CONT, 16'b00000???11110111} :
|
begin
|
|
set_irq_flag = rd_data[6:0];
|
set_irq_flag = rd_data[6:0];
|
end
|
|
|
|
// -----------------------------------------------------------------------
|
// -----------------------------------------------------------------------
|
// Instruction Group -- Special Move instructions
|
// Instruction Group -- Special Move instructions
|
// -----------------------------------------------------------------------
|
// -----------------------------------------------------------------------
|
|
|
| Line 1307... |
Line 1305... |
// Instruction = BCC REL9, Op Code = 0 0 1 0 0 0 0 REL9
|
// Instruction = BCC REL9, Op Code = 0 0 1 0 0 0 0 REL9
|
// Branch if Carry Cleared
|
// Branch if Carry Cleared
|
// If C = 0, then PC + $0002 + (REL9 << 1) => PC
|
// If C = 0, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0010000?????????} :
|
{CONT, 16'b0010000?????????} :
|
begin
|
|
if (!carry_flag)
|
if (!carry_flag)
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum; // There is a race condition when the default declaration is used
|
next_pc = pc_sum; // There is a race condition when the default declaration is used
|
end
|
end
|
end
|
|
|
|
// Instruction = BCS REL9, Op Code = 0 0 1 0 0 0 1 REL9
|
// Instruction = BCS REL9, Op Code = 0 0 1 0 0 0 1 REL9
|
// Branch if Carry Set
|
// Branch if Carry Set
|
// If C = 1, then PC + $0002 + (REL9 << 1) => PC
|
// If C = 1, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0010001?????????} :
|
{CONT, 16'b0010001?????????} :
|
begin
|
|
if (carry_flag)
|
if (carry_flag)
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum;
|
next_pc = pc_sum;
|
end
|
end
|
end
|
|
|
|
// Instruction = BNE REL9, Op Code = 0 0 1 0 0 1 0 REL9
|
// Instruction = BNE REL9, Op Code = 0 0 1 0 0 1 0 REL9
|
// Branch if Not Equal
|
// Branch if Not Equal
|
// If Z = 0, then PC + $0002 + (REL9 << 1) => PC
|
// If Z = 0, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0010010?????????} :
|
{CONT, 16'b0010010?????????} :
|
begin
|
|
if (!zero_flag)
|
if (!zero_flag)
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum;
|
next_pc = pc_sum;
|
end
|
end
|
end
|
|
|
|
// Instruction = BEQ REL9, Op Code = 0 0 1 0 0 1 1 REL9
|
// Instruction = BEQ REL9, Op Code = 0 0 1 0 0 1 1 REL9
|
// Branch if Equal
|
// Branch if Equal
|
// If Z = 1, then PC + $0002 + (REL9 << 1) => PC
|
// If Z = 1, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0010011?????????} :
|
{CONT, 16'b0010011?????????} :
|
begin
|
|
if (zero_flag)
|
if (zero_flag)
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum;
|
next_pc = pc_sum;
|
end
|
end
|
end
|
|
|
|
// Instruction = BPL REL9, Op Code = 0 0 1 0 1 0 0 REL9
|
// Instruction = BPL REL9, Op Code = 0 0 1 0 1 0 0 REL9
|
// Branch if Plus
|
// Branch if Plus
|
// If N = 0, then PC + $0002 + (REL9 << 1) => PC
|
// If N = 0, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0010100?????????} :
|
{CONT, 16'b0010100?????????} :
|
begin
|
|
if (!negative_flag)
|
if (!negative_flag)
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum;
|
next_pc = pc_sum;
|
end
|
end
|
end
|
|
|
|
// Instruction = BMI REL9, Op Code = 0 0 1 0 1 0 1 REL9
|
// Instruction = BMI REL9, Op Code = 0 0 1 0 1 0 1 REL9
|
// Branch if Minus
|
// Branch if Minus
|
// If N = 1, then PC + $0002 + (REL9 << 1) => PC
|
// If N = 1, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0010101?????????} :
|
{CONT, 16'b0010101?????????} :
|
begin
|
|
if (negative_flag)
|
if (negative_flag)
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum;
|
next_pc = pc_sum;
|
end
|
end
|
end
|
|
|
|
// Instruction = BVC REL9, Op Code = 0 0 1 0 1 1 0 REL9
|
// Instruction = BVC REL9, Op Code = 0 0 1 0 1 1 0 REL9
|
// Branch if Overflow Cleared
|
// Branch if Overflow Cleared
|
// If V = 0, then PC + $0002 + (REL9 << 1) => PC
|
// If V = 0, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0010110?????????} :
|
{CONT, 16'b0010110?????????} :
|
begin
|
|
if (!overflow_flag)
|
if (!overflow_flag)
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum;
|
next_pc = pc_sum;
|
end
|
end
|
end
|
|
|
|
// Instruction = BVS REL9, Op Code = 0 0 1 0 1 1 1 REL9
|
// Instruction = BVS REL9, Op Code = 0 0 1 0 1 1 1 REL9
|
// Branch if Overflow Set
|
// Branch if Overflow Set
|
// If V = 1, then PC + $0002 + (REL9 << 1) => PC
|
// If V = 1, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0010111?????????} :
|
{CONT, 16'b0010111?????????} :
|
begin
|
|
if (overflow_flag)
|
if (overflow_flag)
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum;
|
next_pc = pc_sum;
|
end
|
end
|
end
|
|
|
|
// Instruction = BHI REL9, Op Code = 0 0 1 1 0 0 0 REL9
|
// Instruction = BHI REL9, Op Code = 0 0 1 1 0 0 0 REL9
|
// Branch if Higher
|
// Branch if Higher
|
// If C | Z = 0, then PC + $0002 + (REL9 << 1) => PC
|
// If C | Z = 0, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0011000?????????} :
|
{CONT, 16'b0011000?????????} :
|
begin
|
|
if (!(carry_flag || zero_flag))
|
if (!(carry_flag || zero_flag))
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum;
|
next_pc = pc_sum;
|
end
|
end
|
end
|
|
|
|
// Instruction = BLS REL9, Op Code = 0 0 1 1 0 0 1 REL9
|
// Instruction = BLS REL9, Op Code = 0 0 1 1 0 0 1 REL9
|
// Branch if Lower or Same
|
// Branch if Lower or Same
|
// If C | Z = 1, then PC + $0002 + (REL9 << 1) => PC
|
// If C | Z = 1, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0011001?????????} :
|
{CONT, 16'b0011001?????????} :
|
begin
|
|
if (carry_flag || zero_flag)
|
if (carry_flag || zero_flag)
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum;
|
next_pc = pc_sum;
|
end
|
end
|
end
|
|
|
|
// Instruction = BGE REL9, Op Code = 0 0 1 1 0 1 0 REL9
|
// Instruction = BGE REL9, Op Code = 0 0 1 1 0 1 0 REL9
|
// Branch if Greater than or Equal to Zero
|
// Branch if Greater than or Equal to Zero
|
// If N ^ V = 0, then PC + $0002 + (REL9 << 1) => PC
|
// If N ^ V = 0, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0011010?????????} :
|
{CONT, 16'b0011010?????????} :
|
begin
|
|
if (!(negative_flag ^ overflow_flag))
|
if (!(negative_flag ^ overflow_flag))
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum;
|
next_pc = pc_sum;
|
end
|
end
|
end
|
|
|
|
// Instruction = BLT REL9, Op Code = 0 0 1 1 0 1 1 REL9
|
// Instruction = BLT REL9, Op Code = 0 0 1 1 0 1 1 REL9
|
// Branch if Lower than Zero
|
// Branch if Lower than Zero
|
// If N ^ V = 1, then PC + $0002 + (REL9 << 1) => PC
|
// If N ^ V = 1, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0011011?????????} :
|
{CONT, 16'b0011011?????????} :
|
begin
|
|
if (negative_flag ^ overflow_flag)
|
if (negative_flag ^ overflow_flag)
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum;
|
next_pc = pc_sum;
|
end
|
end
|
end
|
|
|
|
// Instruction = BGT REL9, Op Code = 0 0 1 1 1 0 0 REL9
|
// Instruction = BGT REL9, Op Code = 0 0 1 1 1 0 0 REL9
|
// Branch if Greater than Zero
|
// Branch if Greater than Zero
|
// If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) => PC
|
// If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0011100?????????} :
|
{CONT, 16'b0011100?????????} :
|
begin
|
|
if (!(zero_flag || (negative_flag ^ overflow_flag)))
|
if (!(zero_flag || (negative_flag ^ overflow_flag)))
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum;
|
next_pc = pc_sum;
|
end
|
end
|
end
|
|
|
|
// Instruction = BLE REL9, Op Code = 0 0 1 1 1 0 1 REL9
|
// Instruction = BLE REL9, Op Code = 0 0 1 1 1 0 1 REL9
|
// Branch if Less or Equal to Zero
|
// Branch if Less or Equal to Zero
|
// If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) => PC
|
// If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) => PC
|
// Cycles - PP/P
|
// Cycles - PP/P
|
{CONT, 16'b0011101?????????} :
|
{CONT, 16'b0011101?????????} :
|
begin
|
|
if (zero_flag || (negative_flag ^ overflow_flag))
|
if (zero_flag || (negative_flag ^ overflow_flag))
|
begin
|
begin
|
next_cpu_state = S_STALL;
|
next_cpu_state = S_STALL;
|
load_next_inst = 1'b0;
|
load_next_inst = 1'b0;
|
pc_incr_mux = jump_offset;
|
pc_incr_mux = jump_offset;
|
next_pc = pc_sum;
|
next_pc = pc_sum;
|
end
|
end
|
end
|
|
|
|
// Instruction = BRA REL10, Op Code = 0 0 1 1 1 1 REL10
|
// Instruction = BRA REL10, Op Code = 0 0 1 1 1 1 REL10
|
// Branch Always, signed offset
|
// Branch Always, signed offset
|
// PC + $0002 + (REL10 << 1) => PC
|
// PC + $0002 + (REL10 << 1) => PC
|
// Cycles - PP
|
// Cycles - PP
|
| Line 2168... |
Line 2138... |
// Semaphore Bits
|
// Semaphore Bits
|
genvar sem_gen_count;
|
genvar sem_gen_count;
|
generate
|
generate
|
for (sem_gen_count = 0; sem_gen_count < 8; sem_gen_count = sem_gen_count + 1)
|
for (sem_gen_count = 0; sem_gen_count < 8; sem_gen_count = sem_gen_count + 1)
|
begin:semaphore_
|
begin:semaphore_
|
semaphore_bit bit(
|
semaphore_bit sbit(
|
// outputs
|
// outputs
|
.host_status( host_semap[sem_gen_count] ),
|
.host_status( host_semap[sem_gen_count] ),
|
.risc_status( risc_semap[sem_gen_count] ),
|
.risc_status( risc_semap[sem_gen_count] ),
|
// inputs
|
// inputs
|
.risc_clk( risc_clk ),
|
.risc_clk( risc_clk ),
|
