| Line 106... |
Line 106... |
integer j; // Loop counters for decode of XGATE Interrupt Register
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integer j; // Loop counters for decode of XGATE Interrupt Register
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integer k; // Loop counter for Bit Field Insert decode
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integer k; // Loop counter for Bit Field Insert decode
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integer bfi, bfii; // Loop counter for Bit Field Insert function
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integer bfi, bfii; // Loop counter for Bit Field Insert function
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// State machine sequence
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// State machine sequence
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parameter [3:0] //synopsys enum state_info
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localparam [3:0] //synopsys enum state_info
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IDLE = 4'b0000, // waiting for interrupt
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IDLE = 4'b0000, // waiting for interrupt
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CONT = 4'b0001, // Instruction processing state, first state
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CONT = 4'b0001, // Instruction processing state, first state
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S_STALL = 4'b0010, // Simple Stall while updating PC after change of flow
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S_STALL = 4'b0010, // Simple Stall while updating PC after change of flow
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W_STORE = 4'b1101, // Stall while doing memory word write access
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W_STORE = 4'b1101, // Stall while doing memory word write access
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W_LOAD = 4'b0011, // Stall while doing memory word read access
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W_LOAD = 4'b0011, // Stall while doing memory word read access
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| Line 124... |
Line 124... |
BOOT_3 = 4'b1011, //
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BOOT_3 = 4'b1011, //
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CHG_CHID = 4'b1100;
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CHG_CHID = 4'b1100;
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// Semaphore states
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// Semaphore states
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parameter [1:0] NO_LOCK = 2'b00,
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localparam [1:0] NO_LOCK = 2'b00,
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RISC_LOCK = 2'b10,
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RISC_LOCK = 2'b10,
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HOST_LOCK = 2'b11;
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HOST_LOCK = 2'b11;
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reg [ 3:0] cpu_state; // State register for instruction processing
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reg [ 3:0] cpu_state; // State register for instruction processing
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| Line 139... |
Line 139... |
wire [15:0] pc_sum; // Program Counter Adder
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wire [15:0] pc_sum; // Program Counter Adder
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reg [15:0] pc_incr_mux; // Pseudo Register, mux to select the Program Counter Increment value
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reg [15:0] pc_incr_mux; // Pseudo Register, mux to select the Program Counter Increment value
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reg [15:0] next_pc; // Pseudo Register
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reg [15:0] next_pc; // Pseudo Register
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wire [15:0] jump_offset; // Address offset to be added to pc on conditional branch instruction
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wire [15:0] jump_offset; // Address offset to be added to pc on conditional branch instruction
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wire [15:0] bra_offset; // Address offset to be added to pc on branch always instruction
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wire [15:0] bra_offset; // Address offset to be added to pc on branch always instruction
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wire pc_carry; // Carry out bit from pc adder
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wire pc_overflow; // Next pc is out-of-range
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wire pc_underflow; // Next pc is out-of-range
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wire pc_error; // Next pc calculation error
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reg [15:0] alu_result; // Pseudo Register,
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reg [15:0] alu_result; // Pseudo Register,
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reg [15:0] op_code; // Register for instruction being executed
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reg [15:0] op_code; // Register for instruction being executed
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reg ena_rd_low_byte; // Pseudo Register,
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reg ena_rd_low_byte; // Pseudo Register,
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reg ena_rd_high_byte; // Pseudo Register,
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reg ena_rd_high_byte; // Pseudo Register,
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| Line 209... |
Line 213... |
reg [ 1:0] chid_sm_ns; // Pseudo Register for State Machine next state logic,
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reg [ 1:0] chid_sm_ns; // Pseudo Register for State Machine next state logic,
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reg [ 1:0] chid_sm; //
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reg [ 1:0] chid_sm; //
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wire chid_goto_idle; //
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wire chid_goto_idle; //
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// Debug states for change CHID
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// Debug states for change CHID
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parameter [1:0] CHID_IDLE = 2'b00,
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localparam [1:0] CHID_IDLE = 2'b00,
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CHID_TEST = 2'b10,
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CHID_TEST = 2'b10,
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CHID_WAIT = 2'b11;
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CHID_WAIT = 2'b11;
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assign jump_offset = {{6{op_code[8]}}, op_code[8:0], 1'b0};
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assign jump_offset = {{6{op_code[8]}}, op_code[8:0], 1'b0};
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assign bra_offset = {{5{op_code[9]}}, op_code[9:0], 1'b0};
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assign bra_offset = {{5{op_code[9]}}, op_code[9:0], 1'b0};
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assign pc_sum = program_counter + pc_incr_mux;
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assign pc_overflow = pc_carry & !pc_incr_mux[15];
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assign pc_underflow = !pc_carry & pc_incr_mux[15];
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assign pc_error = pc_overflow || pc_underflow;
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assign {pc_carry, pc_sum} = program_counter + pc_incr_mux;
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assign xgate_address = data_access ? data_address : program_counter;
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assign xgate_address = data_access ? data_address : program_counter;
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//assign mem_access = data_access || load_next_inst || start_thread;
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//assign mem_access = data_access || load_next_inst || start_thread;
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assign mem_access = data_access || load_next_inst || (cpu_state == CONT) ||
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assign mem_access = data_access || load_next_inst || (cpu_state == CONT) ||
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| Line 238... |
Line 246... |
assign cpu_is_idle = (cpu_state == IDLE);
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assign cpu_is_idle = (cpu_state == IDLE);
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assign perif_wrt_ena = (cpu_is_idle && ~xge) || debug_active;
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assign perif_wrt_ena = (cpu_is_idle && ~xge) || debug_active;
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// Decode register select for RD and RS
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// Decode register select for RD and RS
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always @*
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always @*
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begin
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case (op_code[10:8]) // synopsys parallel_case
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case (op_code[10:8]) // synopsys parallel_case
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3'b001 : rd_data = xgr1;
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3'b001 : rd_data = xgr1;
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3'b010 : rd_data = xgr2;
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3'b010 : rd_data = xgr2;
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3'b011 : rd_data = xgr3;
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3'b011 : rd_data = xgr3;
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3'b100 : rd_data = xgr4;
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3'b100 : rd_data = xgr4;
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3'b101 : rd_data = xgr5;
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3'b101 : rd_data = xgr5;
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3'b110 : rd_data = xgr6;
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3'b110 : rd_data = xgr6;
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3'b111 : rd_data = xgr7;
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3'b111 : rd_data = xgr7;
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default : rd_data = 16'h0; // XGR0 is always Zero
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default : rd_data = 16'h0; // XGR0 is always Zero
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endcase
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endcase
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end
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assign wrt_reg_sel = (cpu_state == BOOT_3) ? 3'b001 :
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assign wrt_reg_sel = (cpu_state == BOOT_3) ? 3'b001 :
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(sel_rd_field ? op_code[10:8] : op_code[4:2]);
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(sel_rd_field ? op_code[10:8] : op_code[4:2]);
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// Decode register write select for eather RD or RI/RS2
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// Decode register write select for eather RD or RI/RS2
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| Line 310... |
Line 316... |
// Software Error Interrupt Latch
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// Software Error Interrupt Latch
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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software_error <= 1'b0;
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software_error <= 1'b0;
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else
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else
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software_error <= addr_error || op_code_error ||
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software_error <= addr_error || op_code_error || pc_error ||
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(brk_set_dbg && brk_irq_ena) || (software_error && !xgsweif_c);
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(brk_set_dbg && brk_irq_ena) || (software_error && !xgsweif_c);
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assign xg_sw_irq = software_error && xgie;
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assign xg_sw_irq = software_error && xgie;
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// Latch the need to go to debug state set by xgdb
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// Latch the need to go to debug state set by xgdb
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| Line 336... |
Line 342... |
debug_active <= 1'b0;
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debug_active <= 1'b0;
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debug_edge <= 0;
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debug_edge <= 0;
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end
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end
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else
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else
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begin
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begin
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debug_active <= !xgdbg_clear && (cmd_dbg ||
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debug_active <= !xgdbg_clear && (cmd_dbg || pc_error ||
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brk_set_dbg || op_code_error || debug_active);
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brk_set_dbg || op_code_error || debug_active);
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debug_edge <= debug_active;
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debug_edge <= debug_active;
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end
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end
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assign debug_ack = debug_active && !debug_edge; // Posedge of debug_active
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assign debug_ack = debug_active && !debug_edge; // Posedge of debug_active
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| Line 359... |
Line 365... |
// CPU State Register
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// CPU State Register
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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cpu_state <= IDLE;
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cpu_state <= IDLE;
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else
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else
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cpu_state <= (mem_req_ack || stm_auto_advance) ? next_cpu_state : cpu_state;
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cpu_state <= (mem_req_ack || stm_auto_advance || ~xge) ? next_cpu_state : cpu_state;
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// CPU Instruction Register
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// CPU Instruction Register
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always @(posedge risc_clk or negedge async_rst_b)
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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op_code <= 16'h0000;
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op_code <= 16'h0000;
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| Line 457... |
Line 463... |
begin
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begin
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xgif_d[j] = xgif_status[j] || (set_irq_flag == j);
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xgif_d[j] = xgif_status[j] || (set_irq_flag == j);
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j = j + 1;
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j = j + 1;
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end
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end
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if (clear_xgif_0)
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if (clear_xgif_0)
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xgif_d[15: 1] = ~clear_xgif_data & xgif_status[15: 1];
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xgif_d[15: 1] = ~clear_xgif_data[15:1] & xgif_status[15:1];
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if (clear_xgif_1)
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if (clear_xgif_1)
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xgif_d[31:16] = ~clear_xgif_data & xgif_status[31:16];
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xgif_d[31:16] = ~clear_xgif_data & xgif_status[31:16];
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if (clear_xgif_2)
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if (clear_xgif_2)
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xgif_d[47:32] = ~clear_xgif_data & xgif_status[47:32];
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xgif_d[47:32] = ~clear_xgif_data & xgif_status[47:32];
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if (clear_xgif_3)
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if (clear_xgif_3)
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| Line 2121... |
Line 2127... |
);
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);
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// Three to Eight line decoder
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// Three to Eight line decoder
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always @*
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always @*
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case (semaph_risc) // synopsys parallel_case
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case (semaph_risc) // synopsys parallel_case
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4'h0 : semap_risc_bit = 8'b0000_0001;
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3'h0 : semap_risc_bit = 8'b0000_0001;
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4'h1 : semap_risc_bit = 8'b0000_0010;
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3'h1 : semap_risc_bit = 8'b0000_0010;
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4'h2 : semap_risc_bit = 8'b0000_0100;
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3'h2 : semap_risc_bit = 8'b0000_0100;
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4'h3 : semap_risc_bit = 8'b0000_1000;
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3'h3 : semap_risc_bit = 8'b0000_1000;
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4'h4 : semap_risc_bit = 8'b0001_0000;
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3'h4 : semap_risc_bit = 8'b0001_0000;
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4'h5 : semap_risc_bit = 8'b0010_0000;
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3'h5 : semap_risc_bit = 8'b0010_0000;
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4'h6 : semap_risc_bit = 8'b0100_0000;
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3'h6 : semap_risc_bit = 8'b0100_0000;
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4'h7 : semap_risc_bit = 8'b1000_0000;
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3'h7 : semap_risc_bit = 8'b1000_0000;
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endcase
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endcase
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assign semaph_stat = |risc_semap;
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assign semaph_stat = |risc_semap;
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// Semaphore Bits
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// Semaphore Bits
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| Line 2391... |
Line 2397... |
semap_state <= NO_LOCK;
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semap_state <= NO_LOCK;
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else
|
else
|
semap_state <= next_semap_state;
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semap_state <= next_semap_state;
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|
always @*
|
always @*
|
begin
|
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case(semap_state)
|
case(semap_state)
|
NO_LOCK:
|
NO_LOCK:
|
begin
|
begin
|
if (host_wrt && host_bit_mask && host_bit)
|
if (host_wrt && host_bit_mask && host_bit)
|
next_semap_state = HOST_LOCK;
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next_semap_state = HOST_LOCK;
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| Line 2419... |
Line 2424... |
next_semap_state = HOST_LOCK;
|
next_semap_state = HOST_LOCK;
|
end
|
end
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default:
|
default:
|
next_semap_state = NO_LOCK;
|
next_semap_state = NO_LOCK;
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endcase
|
endcase
|
end
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endmodule // semaphore_bit
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endmodule // semaphore_bit
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No newline at end of file
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No newline at end of file
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