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https://opencores.org/ocsvn/xgate/xgate/trunk
[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Diff between revs 89 and 96
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| Rev 89 |
Rev 96 |
| Line 160... |
Line 160... |
wire ss_mem_ack; // WISHBONE Bus has granted single step memory access
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wire ss_mem_ack; // WISHBONE Bus has granted single step memory access
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wire [ 7:0] host_semap; // Semaphore status for host
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wire [ 7:0] host_semap; // Semaphore status for host
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wire write_mem_strb_l; // Strobe for writing low data byte
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wire write_mem_strb_l; // Strobe for writing low data byte
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wire write_mem_strb_h; // Strobe for writing high data bye
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wire write_mem_strb_h; // Strobe for writing high data bye
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wire sync_reset;
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wire async_rst_b;
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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// Wishbone Slave Bus interface
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// Wishbone Slave Bus interface
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xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
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xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
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.SINGLE_CYCLE(SINGLE_CYCLE),
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.SINGLE_CYCLE(SINGLE_CYCLE),
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| Line 174... |
Line 176... |
.wbs_err_o( wbs_err_o ),
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.wbs_err_o( wbs_err_o ),
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.wbs_clk_i( wbs_clk_i ),
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.wbs_clk_i( wbs_clk_i ),
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.wbs_rst_i( wbs_rst_i ),
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.wbs_rst_i( wbs_rst_i ),
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.arst_i( arst_i ),
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.arst_i( arst_i ),
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.wbs_adr_i( wbs_adr_i ),
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.wbs_adr_i( wbs_adr_i ),
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.wbs_dat_i( wbs_dat_i ),
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.wbs_we_i( wbs_we_i ),
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.wbs_we_i( wbs_we_i ),
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.wbs_stb_i( wbs_stb_i ),
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.wbs_stb_i( wbs_stb_i ),
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.wbs_cyc_i( wbs_cyc_i ),
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.wbs_cyc_i( wbs_cyc_i ),
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.wbs_sel_i( wbs_sel_i ),
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.wbs_sel_i( wbs_sel_i ),
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| Line 393... |
Line 394... |
.wbm_cyc_o( wbm_cyc_o ),
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.wbm_cyc_o( wbm_cyc_o ),
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.wbm_sel_o( wbm_sel_o ),
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.wbm_sel_o( wbm_sel_o ),
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.wbm_adr_o( wbm_adr_o ),
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.wbm_adr_o( wbm_adr_o ),
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.wbm_dat_i( wbm_dat_i ),
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.wbm_dat_i( wbm_dat_i ),
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.wbm_ack_i( wbm_ack_i ),
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.wbm_ack_i( wbm_ack_i ),
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.wbs_clk_i( wbs_clk_i ),
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.wbs_rst_i( wbs_rst_i ),
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.arst_i( arst_i ),
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// XGATE Control Signals
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// XGATE Control Signals
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.risc_clk( risc_clk ),
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.risc_clk( risc_clk ),
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.async_rst_b( async_rst_b ),
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.async_rst_b( async_rst_b ),
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.xge( xge ),
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.xge( xge ),
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.mem_access( mem_access ),
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.mem_access( mem_access ),
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