| Line 124... |
Line 124... |
wire clear_xgif_0; // Strobe for decode to clear interrupt flag bank 0
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wire clear_xgif_0; // Strobe for decode to clear interrupt flag bank 0
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wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag
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wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag
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|
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wire xge; // XGATE Module Enable
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wire xge; // XGATE Module Enable
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wire xgfrz; // Stop XGATE in Freeze Mode
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wire xgfrz; // Stop XGATE in Freeze Mode
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wire xgdbg; // XGATE Debug Mode
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wire xgdbg_set; // Enter XGATE Debug Mode
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wire xgdbg_clear; // Leave XGATE Debug Mode
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wire xgss; // XGATE Single Step
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wire xgss; // XGATE Single Step
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wire xgsweif_c; // Clear XGATE Software Error Interrupt FLag
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wire xgsweif_c; // Clear XGATE Software Error Interrupt FLag
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wire xgie; // XGATE Interrupt Enable
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wire xgie; // XGATE Interrupt Enable
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wire [ 6:0] int_req; // Encoded interrupt request
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wire [ 6:0] int_req; // Encoded interrupt request
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wire [ 6:0] xgchid; // Channel actively being processed
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wire [ 6:0] xgchid; // Channel actively being processed
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| Line 228... |
Line 229... |
.MAX_CHANNEL(MAX_CHANNEL))
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.MAX_CHANNEL(MAX_CHANNEL))
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regs(
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regs(
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// outputs
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// outputs
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.xge( xge ),
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.xge( xge ),
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.xgfrz( xgfrz ),
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.xgfrz( xgfrz ),
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.xgdbg( xgdbg ),
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.xgdbg_set( xgdbg_set ),
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.xgdbg_clear( xgdbg_clear ),
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.xgss( xgss ),
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.xgss( xgss ),
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.xgsweif_c( xgsweif_c ),
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.xgsweif_c( xgsweif_c ),
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.xgie( xgie ),
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.xgie( xgie ),
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.brk_irq_ena( brk_irq_ena ),
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.brk_irq_ena( brk_irq_ena ),
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.xgvbr( xgvbr ),
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.xgvbr( xgvbr ),
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| Line 302... |
Line 304... |
.async_rst_b( async_rst_b ),
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.async_rst_b( async_rst_b ),
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.read_mem_data( read_mem_data ),
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.read_mem_data( read_mem_data ),
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.mem_req_ack( mem_req_ack ),
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.mem_req_ack( mem_req_ack ),
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.xge( xge ),
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.xge( xge ),
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.xgfrz( xgfrz ),
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.xgfrz( xgfrz ),
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.xgdbg( xgdbg ),
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.xgdbg_set( xgdbg_set ),
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.xgdbg_clear( xgdbg_clear ),
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.xgss( xgss ),
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.xgss( xgss ),
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.xgvbr( xgvbr ),
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.xgvbr( xgvbr ),
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.int_req( int_req ),
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.int_req( int_req ),
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.xgie( xgie ),
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.xgie( xgie ),
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.brk_irq_ena( brk_irq_ena ),
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.brk_irq_ena( brk_irq_ena ),
|
