| Line 70... |
Line 70... |
output write_mem_strb_h, // Strobe for writing high data bye
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output write_mem_strb_h, // Strobe for writing high data bye
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output xg_sw_irq, // Xgate Software interrupt
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output xg_sw_irq, // Xgate Software interrupt
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output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag
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output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag
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input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt request
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input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt request
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input risc_clk, // Clock for RISC core
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input risc_clk, // Clock for RISC core
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input debug_mode_i, // Force RISC core into debug mode
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input secure_mode_i, // Limit host asscess to Xgate RISC registers
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input scantestmode // Chip in in scan test mode
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input scantestmode // Chip in in scan test mode
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);
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);
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|
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wire zero_flag;
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wire zero_flag;
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wire negative_flag;
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wire negative_flag;
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| Line 132... |
Line 134... |
wire xgss; // XGATE Single Step
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wire xgss; // XGATE Single Step
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wire xgsweif_c; // Clear XGATE Software Error Interrupt FLag
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wire xgsweif_c; // Clear XGATE Software Error Interrupt FLag
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wire xgie; // XGATE Interrupt Enable
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wire xgie; // XGATE Interrupt Enable
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wire [ 6:0] int_req; // Encoded interrupt request
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wire [ 6:0] int_req; // Encoded interrupt request
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wire [ 6:0] xgchid; // Channel actively being processed
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wire [ 6:0] xgchid; // Channel actively being processed
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wire [127:0] xgif_status; // Status bits of interrupt output flags that have been set
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wire [15:1] xgvbr; // XGATE vector Base Address Register
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wire [15:1] xgvbr; // XGATE vector Base Address Register
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wire brk_irq_ena; // Enable BRK instruction to generate interrupt
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wire brk_irq_ena; // Enable BRK instruction to generate interrupt
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|
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wire [15:0] xgate_address; //
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wire [15:0] xgate_address; //
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wire [15:0] write_mem_data; //
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wire [15:0] write_mem_data; //
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| Line 147... |
Line 150... |
wire [ 7:0] host_semap; // Semaphore status for host
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wire [ 7:0] host_semap; // Semaphore status for host
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// wire [15:0] write_mem_data;
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// wire [15:0] write_mem_data;
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// wire [15:0] read_mem_data;
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// wire [15:0] read_mem_data;
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// wire [15:0] perif_data;
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// wire [15:0] perif_data;
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|
|
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assign xgif = xgif_status[MAX_CHANNEL:0];
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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// Wishbone Slave Bus interface
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// Wishbone Slave Bus interface
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xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
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xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
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.SINGLE_CYCLE(SINGLE_CYCLE))
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.SINGLE_CYCLE(SINGLE_CYCLE))
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wishbone_s(
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wishbone_s(
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| Line 207... |
Line 210... |
xgate_address, // XGPC
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xgate_address, // XGPC
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{12'h000, negative_flag, zero_flag, overflow_flag, carry_flag}, // XGCCR
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{12'h000, negative_flag, zero_flag, overflow_flag, carry_flag}, // XGCCR
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16'b0, // Reserved
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16'b0, // Reserved
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{8'h00, host_semap}, // XGSEM
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{8'h00, host_semap}, // XGSEM
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{8'h00, xgswt}, // XGSWT
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{8'h00, xgswt}, // XGSWT
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xgif[ 15: 0], // XGIF_0
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xgif_status[ 15: 0], // XGIF_0
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xgif[ 31: 16], // XGIF_1
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xgif_status[ 31: 16], // XGIF_1
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xgif[ 47: 32], // XGIF_2
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xgif_status[ 47: 32], // XGIF_2
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xgif[ 63: 48], // XGIF_3
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xgif_status[ 63: 48], // XGIF_3
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xgif[ 79: 64], // XGIF_4
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xgif_status[ 79: 64], // XGIF_4
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xgif[ 95: 80], // XGIF_5
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xgif_status[ 95: 80], // XGIF_5
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xgif[111: 96], // XGIF_6
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xgif_status[111: 96], // XGIF_6
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xgif[127:112], // XGIF_7
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xgif_status[127:112], // XGIF_7
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{xgvbr[15:1], 1'b0}, // XGVBR
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{xgvbr[15:1], 1'b0}, // XGVBR
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xgisp30, // Reserved
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xgisp30, // Reserved
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xgisp74, // Reserved
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xgisp74, // Reserved
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{8'b0, 1'b0, xgchid}, // XGCHID
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{8'b0, 1'b0, xgchid}, // XGCHID
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{8'b0, xge, xgfrz, debug_active, 1'b0, 1'b0, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL
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{8'b0, xge, xgfrz, debug_active, 1'b0, 1'b0, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL
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| Line 292... |
Line 295... |
.xgr3( xgr3 ),
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.xgr3( xgr3 ),
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.xgr4( xgr4 ),
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.xgr4( xgr4 ),
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.xgr5( xgr5 ),
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.xgr5( xgr5 ),
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.xgr6( xgr6 ),
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.xgr6( xgr6 ),
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.xgr7( xgr7 ),
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.xgr7( xgr7 ),
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.xgif( xgif ),
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.xgif_status( xgif_status ),
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.debug_active( debug_active ),
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.debug_active( debug_active ),
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.xg_sw_irq( xg_sw_irq ),
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.xg_sw_irq( xg_sw_irq ),
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|
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// inputs
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// inputs
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.risc_clk( risc_clk ),
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.risc_clk( risc_clk ),
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| Line 306... |
Line 309... |
.mem_req_ack( mem_req_ack ),
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.mem_req_ack( mem_req_ack ),
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.xge( xge ),
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.xge( xge ),
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.xgfrz( xgfrz ),
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.xgfrz( xgfrz ),
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.xgdbg_set( xgdbg_set ),
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.xgdbg_set( xgdbg_set ),
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.xgdbg_clear( xgdbg_clear ),
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.xgdbg_clear( xgdbg_clear ),
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.debug_mode_i(debug_mode_i),
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.xgss( xgss ),
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.xgss( xgss ),
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.xgvbr( xgvbr ),
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.xgvbr( xgvbr ),
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.int_req( int_req ),
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.int_req( int_req ),
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.xgie( xgie ),
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.xgie( xgie ),
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.brk_irq_ena( brk_irq_ena ),
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.brk_irq_ena( brk_irq_ena ),
|
