| Line 141... |
Line 141... |
wire brk_irq_ena; // Enable BRK instruction to generate interrupt
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wire brk_irq_ena; // Enable BRK instruction to generate interrupt
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wire [15:0] xgate_address; //
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wire [15:0] xgate_address; //
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wire [15:0] write_mem_data; //
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wire [15:0] write_mem_data; //
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wire [15:0] read_mem_data; //
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wire [15:0] read_mem_data; //
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wire mem_access; //
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wire mem_req_ack; //
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wire mem_req_ack; //
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wire debug_active; // RISC state machine in Debug mode
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wire debug_active; // RISC state machine in Debug mode
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wire [ 7:0] host_semap; // Semaphore status for host
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wire [ 7:0] host_semap; // Semaphore status for host
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| Line 298... |
Line 299... |
.xgr6( xgr6 ),
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.xgr6( xgr6 ),
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.xgr7( xgr7 ),
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.xgr7( xgr7 ),
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.xgif_status( xgif_status ),
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.xgif_status( xgif_status ),
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.debug_active( debug_active ),
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.debug_active( debug_active ),
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.xg_sw_irq( xg_sw_irq ),
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.xg_sw_irq( xg_sw_irq ),
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.mem_access( mem_access ),
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// inputs
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// inputs
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.risc_clk( risc_clk ),
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.risc_clk( risc_clk ),
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.perif_data( wbs_dat_i ),
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.perif_data( wbs_dat_i ),
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.async_rst_b( async_rst_b ),
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.async_rst_b( async_rst_b ),
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| Line 363... |
Line 365... |
.wbm_ack_i( wbm_ack_i ),
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.wbm_ack_i( wbm_ack_i ),
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.wbs_clk_i( wbs_clk_i ),
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.wbs_clk_i( wbs_clk_i ),
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.wbs_rst_i( wbs_rst_i ),
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.wbs_rst_i( wbs_rst_i ),
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.arst_i( arst_i ),
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.arst_i( arst_i ),
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// XGATE Control Signals
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// XGATE Control Signals
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.xge( xge ),
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.mem_access( mem_access ),
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.read_mem_data( read_mem_data ),
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.read_mem_data( read_mem_data ),
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.xgate_address( xgate_address ),
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.xgate_address( xgate_address ),
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.mem_req_ack( mem_req_ack ),
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.mem_req_ack( mem_req_ack ),
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.write_mem_strb_l( write_mem_strb_l ),
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.write_mem_strb_l( write_mem_strb_l ),
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.write_mem_strb_h( write_mem_strb_h ),
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.write_mem_strb_h( write_mem_strb_h ),
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