| Line 47... |
Line 47... |
output [DWIDTH-1:0] wbs_dat_o, // databus output
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output [DWIDTH-1:0] wbs_dat_o, // databus output
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output wbs_ack_o, // bus cycle acknowledge output
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output wbs_ack_o, // bus cycle acknowledge output
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input wbs_clk_i, // master clock input
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input wbs_clk_i, // master clock input
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input wbs_rst_i, // synchronous active high reset
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input wbs_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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input arst_i, // asynchronous reset
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input [4:0] wbs_adr_i, // lower address bits
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input [5:1] wbs_adr_i, // lower address bits
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input wbs_we_i, // write enable input
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input wbs_we_i, // write enable input
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input wbs_stb_i, // stobe/core select signal
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input wbs_stb_i, // stobe/core select signal
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input wbs_cyc_i, // valid bus cycle input
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input wbs_cyc_i, // valid bus cycle input
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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| Line 94... |
Line 94... |
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wire write_xgmctl; // Write Strobe for XGMCTL register
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wire write_xgmctl; // Write Strobe for XGMCTL register
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wire write_xgchid; // Write Strobe for XGCHID register
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wire write_xgchid; // Write Strobe for XGCHID register
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wire write_xgisp74; // Write Strobe for XGISP74 register
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wire write_xgisp74; // Write Strobe for XGISP74 register
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wire write_xgisp30; // Write Strobe for XGISP30 register
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wire write_xgisp30; // Write Strobe for XGISP30 register
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wire write_xgvbr; // Write Strobe for XGVBR_LO register
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wire [1:0] write_xgvbr; // Write Strobe for XGVBR register
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wire write_xgif_7; // Write Strobe for Interrupt Flag Register 7
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wire [1:0] write_xgif_7; // Write Strobe for Interrupt Flag Register 7
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wire write_xgif_6; // Write Strobe for Interrupt Flag Register 6
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wire [1:0] write_xgif_6; // Write Strobe for Interrupt Flag Register 6
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wire write_xgif_5; // Write Strobe for Interrupt Flag Register 5
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wire [1:0] write_xgif_5; // Write Strobe for Interrupt Flag Register 5
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wire write_xgif_4; // Write Strobe for Interrupt Flag Register 4
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wire [1:0] write_xgif_4; // Write Strobe for Interrupt Flag Register 4
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wire write_xgif_3; // Write Strobe for Interrupt Flag Register 3
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wire [1:0] write_xgif_3; // Write Strobe for Interrupt Flag Register 3
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wire write_xgif_2; // Write Strobe for Interrupt Flag Register 2
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wire [1:0] write_xgif_2; // Write Strobe for Interrupt Flag Register 2
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wire write_xgif_1; // Write Strobe for Interrupt Flag Register 1
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wire [1:0] write_xgif_1; // Write Strobe for Interrupt Flag Register 1
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wire write_xgif_0; // Write Strobe for Interrupt Flag Register 0
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wire [1:0] write_xgif_0; // Write Strobe for Interrupt Flag Register 0
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wire write_xgswt; // Write Strobe for XGSWT register
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wire write_xgswt; // Write Strobe for XGSWT register
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wire write_xgsem; // Write Strobe for XGSEM register
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wire write_xgsem; // Write Strobe for XGSEM register
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wire write_xgccr; // Write Strobe for XGATE Condition Code Register
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wire write_xgccr; // Write Strobe for XGATE Condition Code Register
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wire write_xgpc; // Write Strobe for XGATE Program Counter
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wire [1:0] write_xgpc; // Write Strobe for XGATE Program Counter
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wire write_xgr7; // Write Strobe for XGATE Data Register R7
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wire [1:0] write_xgr7; // Write Strobe for XGATE Data Register R7
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wire write_xgr6; // Write Strobe for XGATE Data Register R6
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wire [1:0] write_xgr6; // Write Strobe for XGATE Data Register R6
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wire write_xgr5; // Write Strobe for XGATE Data Register R5
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wire [1:0] write_xgr5; // Write Strobe for XGATE Data Register R5
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wire write_xgr4; // Write Strobe for XGATE Data Register R4
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wire [1:0] write_xgr4; // Write Strobe for XGATE Data Register R4
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wire write_xgr3; // Write Strobe for XGATE Data Register R3
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wire [1:0] write_xgr3; // Write Strobe for XGATE Data Register R3
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wire write_xgr2; // Write Strobe for XGATE Data Register R2
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wire [1:0] write_xgr2; // Write Strobe for XGATE Data Register R2
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wire write_xgr1; // Write Strobe for XGATE Data Register R1
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wire [1:0] write_xgr1; // Write Strobe for XGATE Data Register R1
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wire clear_xgif_7; // Strobe for decode to clear interrupt flag bank 7
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wire clear_xgif_7; // Strobe for decode to clear interrupt flag bank 7
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wire clear_xgif_6; // Strobe for decode to clear interrupt flag bank 6
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wire clear_xgif_6; // Strobe for decode to clear interrupt flag bank 6
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wire clear_xgif_5; // Strobe for decode to clear interrupt flag bank 5
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wire clear_xgif_5; // Strobe for decode to clear interrupt flag bank 5
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wire clear_xgif_4; // Strobe for decode to clear interrupt flag bank 4
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wire clear_xgif_4; // Strobe for decode to clear interrupt flag bank 4
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| Line 129... |
Line 129... |
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wire xge; // XGATE Module Enable
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wire xge; // XGATE Module Enable
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wire xgfrz; // Stop XGATE in Freeze Mode
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wire xgfrz; // Stop XGATE in Freeze Mode
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wire xgdbg_set; // Enter XGATE Debug Mode
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wire xgdbg_set; // Enter XGATE Debug Mode
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wire xgdbg_clear; // Leave XGATE Debug Mode
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wire xgdbg_clear; // Leave XGATE Debug Mode
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wire xgfact; // Fake Activity
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wire xgss; // XGATE Single Step
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wire xgss; // XGATE Single Step
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wire xgsweif_c; // Clear XGATE Software Error Interrupt FLag
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wire xgsweif_c; // Clear XGATE Software Error Interrupt FLag
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wire xgie; // XGATE Interrupt Enable
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wire xgie; // XGATE Interrupt Enable
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wire [ 6:0] int_req; // Encoded interrupt request
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wire [ 6:0] int_req; // Encoded interrupt request
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wire [ 6:0] xgchid; // Channel actively being processed
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wire [ 6:0] xgchid; // Channel actively being processed
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| Line 223... |
Line 224... |
xgif_status[127:112], // XGIF_7
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xgif_status[127:112], // XGIF_7
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{xgvbr[15:1], 1'b0}, // XGVBR
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{xgvbr[15:1], 1'b0}, // XGVBR
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xgisp30, // Reserved
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xgisp30, // Reserved
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xgisp74, // Reserved
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xgisp74, // Reserved
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{8'b0, 1'b0, xgchid}, // XGCHID
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{8'b0, 1'b0, xgchid}, // XGCHID
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{8'b0, xge, xgfrz, debug_active, 1'b0, 1'b0, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL
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{8'b0, xge, xgfrz, debug_active, 1'b0, xgfact, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL
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}
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}
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)
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)
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);
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);
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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| Line 237... |
Line 238... |
// outputs
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// outputs
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.xge( xge ),
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.xge( xge ),
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.xgfrz( xgfrz ),
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.xgfrz( xgfrz ),
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.xgdbg_set( xgdbg_set ),
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.xgdbg_set( xgdbg_set ),
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.xgdbg_clear( xgdbg_clear ),
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.xgdbg_clear( xgdbg_clear ),
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.xgfact( xgfact ),
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.xgss( xgss ),
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.xgss( xgss ),
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.xgsweif_c( xgsweif_c ),
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.xgsweif_c( xgsweif_c ),
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.xgie( xgie ),
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.xgie( xgie ),
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.brk_irq_ena( brk_irq_ena ),
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.brk_irq_ena( brk_irq_ena ),
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.xgvbr( xgvbr ),
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.xgvbr( xgvbr ),
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| Line 308... |
Line 310... |
.perif_data( wbs_dat_i ),
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.perif_data( wbs_dat_i ),
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.async_rst_b( async_rst_b ),
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.async_rst_b( async_rst_b ),
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.read_mem_data( read_mem_data ),
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.read_mem_data( read_mem_data ),
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.mem_req_ack( mem_req_ack ),
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.mem_req_ack( mem_req_ack ),
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.xge( xge ),
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.xge( xge ),
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.xgfrz( xgfrz ),
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.xgdbg_set( xgdbg_set ),
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.xgdbg_set( xgdbg_set ),
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.xgdbg_clear( xgdbg_clear ),
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.xgdbg_clear( xgdbg_clear ),
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.debug_mode_i(debug_mode_i),
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.debug_mode_i(debug_mode_i),
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.xgss( xgss ),
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.xgss( xgss ),
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.xgvbr( xgvbr ),
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.xgvbr( xgvbr ),
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