| Line 44... |
Line 44... |
parameter DWIDTH = 16) // Data bus width
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parameter DWIDTH = 16) // Data bus width
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(
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(
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// Wishbone Slave Signals
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// Wishbone Slave Signals
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output [DWIDTH-1:0] wbs_dat_o, // databus output
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output [DWIDTH-1:0] wbs_dat_o, // databus output
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output wbs_ack_o, // bus cycle acknowledge output
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output wbs_ack_o, // bus cycle acknowledge output
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output wbs_err_o, // bus error, lost module select durning wait state
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input wbs_clk_i, // master clock input
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input wbs_clk_i, // master clock input
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input wbs_rst_i, // synchronous active high reset
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input wbs_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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input arst_i, // asynchronous reset
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input [5:1] wbs_adr_i, // lower address bits
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input [5:1] wbs_adr_i, // lower address bits
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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| Line 141... |
Line 142... |
wire [15:0] read_mem_data; //
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wire [15:0] read_mem_data; //
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wire mem_access; //
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wire mem_access; //
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wire mem_req_ack; //
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wire mem_req_ack; //
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wire debug_active; // RISC state machine in Debug mode
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wire debug_active; // RISC state machine in Debug mode
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wire debug_ack; // Clear debug register
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wire single_step; // Pulse to trigger a single instruction execution in debug mode
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wire ss_mem_ack; // WISHBONE Bus has granted single step memory access
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wire [ 7:0] host_semap; // Semaphore status for host
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wire [ 7:0] host_semap; // Semaphore status for host
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// wire [15:0] write_mem_data;
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// wire [15:0] write_mem_data;
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// wire [15:0] read_mem_data;
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// wire [15:0] read_mem_data;
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// wire [15:0] perif_data;
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// wire [15:0] perif_data;
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| Line 155... |
Line 159... |
xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
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xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
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.SINGLE_CYCLE(SINGLE_CYCLE))
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.SINGLE_CYCLE(SINGLE_CYCLE))
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wishbone_s(
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wishbone_s(
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.wbs_dat_o( wbs_dat_o ),
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.wbs_dat_o( wbs_dat_o ),
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.wbs_ack_o( wbs_ack_o ),
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.wbs_ack_o( wbs_ack_o ),
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.wbs_err_o( wbs_err_o ),
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.wbs_clk_i( wbs_clk_i ),
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.wbs_clk_i( wbs_clk_i ),
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.wbs_rst_i( wbs_rst_i ),
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.wbs_rst_i( wbs_rst_i ),
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.arst_i( arst_i ),
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.arst_i( arst_i ),
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.wbs_adr_i( wbs_adr_i ),
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.wbs_adr_i( wbs_adr_i ),
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.wbs_dat_i( wbs_dat_i ),
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.wbs_dat_i( wbs_dat_i ),
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| Line 263... |
Line 268... |
.write_xgif_4( write_xgif_4 ),
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.write_xgif_4( write_xgif_4 ),
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.write_xgif_3( write_xgif_3 ),
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.write_xgif_3( write_xgif_3 ),
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.write_xgif_2( write_xgif_2 ),
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.write_xgif_2( write_xgif_2 ),
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.write_xgif_1( write_xgif_1 ),
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.write_xgif_1( write_xgif_1 ),
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.write_xgif_0( write_xgif_0 ),
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.write_xgif_0( write_xgif_0 ),
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.write_xgswt( write_xgswt )
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.write_xgswt( write_xgswt ),
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.debug_ack( debug_ack )
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);
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);
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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xgate_risc #(.MAX_CHANNEL(MAX_CHANNEL))
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xgate_risc #(.MAX_CHANNEL(MAX_CHANNEL))
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risc(
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risc(
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| Line 289... |
Line 295... |
.xgr5( xgr5 ),
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.xgr5( xgr5 ),
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.xgr6( xgr6 ),
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.xgr6( xgr6 ),
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.xgr7( xgr7 ),
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.xgr7( xgr7 ),
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.xgif_status( xgif_status ),
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.xgif_status( xgif_status ),
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.debug_active( debug_active ),
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.debug_active( debug_active ),
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.debug_ack( debug_ack ),
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.xg_sw_irq( xg_sw_irq ),
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.xg_sw_irq( xg_sw_irq ),
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.mem_access( mem_access ),
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.mem_access( mem_access ),
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.single_step( single_step ),
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// inputs
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// inputs
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.risc_clk( risc_clk ),
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.risc_clk( risc_clk ),
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.perif_data( wbs_dat_i ),
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.perif_data( wbs_dat_i ),
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.async_rst_b( async_rst_b ),
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.async_rst_b( async_rst_b ),
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.read_mem_data( read_mem_data ),
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.read_mem_data( read_mem_data ),
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.mem_req_ack( mem_req_ack ),
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.mem_req_ack( mem_req_ack ),
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.ss_mem_ack( ss_mem_ack ),
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.xge( xge ),
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.xge( xge ),
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.xgdbg_set( xgdbg_set ),
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.xgdbg_set( xgdbg_set ),
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.xgdbg_clear( xgdbg_clear ),
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.xgdbg_clear( xgdbg_clear ),
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.debug_mode_i(debug_mode_i),
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.debug_mode_i(debug_mode_i),
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.xgss( xgss ),
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.xgss( xgss ),
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| Line 355... |
Line 364... |
.wbm_ack_i( wbm_ack_i ),
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.wbm_ack_i( wbm_ack_i ),
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.wbs_clk_i( wbs_clk_i ),
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.wbs_clk_i( wbs_clk_i ),
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.wbs_rst_i( wbs_rst_i ),
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.wbs_rst_i( wbs_rst_i ),
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.arst_i( arst_i ),
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.arst_i( arst_i ),
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// XGATE Control Signals
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// XGATE Control Signals
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.risc_clk( risc_clk ),
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.async_rst_b( async_rst_b ),
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.xge( xge ),
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.xge( xge ),
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.mem_access( mem_access ),
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.mem_access( mem_access ),
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.single_step( single_step ),
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.ss_mem_ack( ss_mem_ack ),
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.read_mem_data( read_mem_data ),
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.read_mem_data( read_mem_data ),
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.xgate_address( xgate_address ),
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.xgate_address( xgate_address ),
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.mem_req_ack( mem_req_ack ),
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.mem_req_ack( mem_req_ack ),
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.write_mem_strb_l( write_mem_strb_l ),
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.write_mem_strb_l( write_mem_strb_l ),
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.write_mem_strb_h( write_mem_strb_h ),
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.write_mem_strb_h( write_mem_strb_h ),
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