| Line 65... |
Line 65... |
output [15:0] wbm_adr_o, // Address bits
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output [15:0] wbm_adr_o, // Address bits
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input [DWIDTH-1:0] wbm_dat_i, // databus input
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input [DWIDTH-1:0] wbm_dat_i, // databus input
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input wbm_ack_i, // bus cycle acknowledge input
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input wbm_ack_i, // bus cycle acknowledge input
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// XGATE IO Signals
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// XGATE IO Signals
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output [ 7:0] xgswt, // XGATE Software Trigger Register
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output [ 7:0] xgswt, // XGATE Software Trigger Register
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output write_mem_strb_l, // Strobe for writing low data byte
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output write_mem_strb_h, // Strobe for writing high data bye
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output xg_sw_irq, // Xgate Software interrupt
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output xg_sw_irq, // Xgate Software interrupt
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output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag
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output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag
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input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt request
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input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt request
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input risc_clk, // Clock for RISC core
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input risc_clk, // Clock for RISC core
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input debug_mode_i, // Force RISC core into debug mode
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input debug_mode_i, // Force RISC core into debug mode
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| Line 147... |
Line 145... |
wire debug_ack; // Clear debug register
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wire debug_ack; // Clear debug register
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wire single_step; // Pulse to trigger a single instruction execution in debug mode
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wire single_step; // Pulse to trigger a single instruction execution in debug mode
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wire ss_mem_ack; // WISHBONE Bus has granted single step memory access
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wire ss_mem_ack; // WISHBONE Bus has granted single step memory access
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wire [ 7:0] host_semap; // Semaphore status for host
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wire [ 7:0] host_semap; // Semaphore status for host
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// wire [15:0] write_mem_data;
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wire write_mem_strb_l; // Strobe for writing low data byte
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// wire [15:0] read_mem_data;
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wire write_mem_strb_h; // Strobe for writing high data bye
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// wire [15:0] perif_data;
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assign xgif = xgif_status[MAX_CHANNEL:0];
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assign xgif = xgif_status[MAX_CHANNEL:0];
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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// Wishbone Slave Bus interface
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// Wishbone Slave Bus interface
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xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
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xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
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