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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module xgate_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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module xgate_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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parameter SINGLE_CYCLE = 1'b0, //
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parameter SINGLE_CYCLE = 1'b0, //
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parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
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parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
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parameter DWIDTH = 16) // Data bus width
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parameter WB_RD_DEFAULT = 0) // WISHBONE Read Bus default state
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(
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(
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// Wishbone Slave Signals
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// Wishbone Slave Signals
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output [DWIDTH-1:0] wbs_dat_o, // databus output
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output [DWIDTH-1:0] wbs_dat_o, // databus output
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output wbs_ack_o, // bus cycle acknowledge output
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output wbs_ack_o, // bus cycle acknowledge output
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output wbs_err_o, // bus error, lost module select durning wait state
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output wbs_err_o, // bus error, lost module select durning wait state
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input wbs_clk_i, // master clock input
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input wbs_clk_i, // master clock input
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input wbs_rst_i, // synchronous active high reset
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input wbs_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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input arst_i, // asynchronous reset
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input [5:1] wbs_adr_i, // lower address bits
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input [6:1] wbs_adr_i, // lower address bits
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input wbs_we_i, // write enable input
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input wbs_we_i, // write enable input
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input wbs_stb_i, // stobe/core select signal
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input wbs_stb_i, // stobe/core select signal
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input wbs_cyc_i, // valid bus cycle input
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input wbs_cyc_i, // valid bus cycle input
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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| Line 66... |
Line 66... |
input [DWIDTH-1:0] wbm_dat_i, // databus input
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input [DWIDTH-1:0] wbm_dat_i, // databus input
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input wbm_ack_i, // bus cycle acknowledge input
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input wbm_ack_i, // bus cycle acknowledge input
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// XGATE IO Signals
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// XGATE IO Signals
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output [ 7:0] xgswt, // XGATE Software Trigger Register
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output [ 7:0] xgswt, // XGATE Software Trigger Register
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output xg_sw_irq, // Xgate Software interrupt
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output xg_sw_irq, // Xgate Software interrupt
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output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag
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output [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag to Host
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input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt request
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input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt request
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input risc_clk, // Clock for RISC core
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input risc_clk, // Clock for RISC core
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input debug_mode_i, // Force RISC core into debug mode
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input debug_mode_i, // Force RISC core into debug mode
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input secure_mode_i, // Limit host asscess to Xgate RISC registers
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input secure_mode_i, // Limit host asscess to Xgate RISC registers
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input scantestmode // Chip in in scan test mode
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input scantestmode // Chip in in scan test mode
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);
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);
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parameter DWIDTH = 16; // Data bus width
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wire zero_flag;
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wire zero_flag;
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wire negative_flag;
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wire negative_flag;
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wire carry_flag;
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wire carry_flag;
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wire overflow_flag;
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wire overflow_flag;
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wire [15:0] xgr1; // XGATE Register #1
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wire [15:0] xgr1; // XGATE Register #1
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wire [1:0] write_xgif_4; // Write Strobe for Interrupt Flag Register 4
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wire [1:0] write_xgif_4; // Write Strobe for Interrupt Flag Register 4
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wire [1:0] write_xgif_3; // Write Strobe for Interrupt Flag Register 3
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wire [1:0] write_xgif_3; // Write Strobe for Interrupt Flag Register 3
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wire [1:0] write_xgif_2; // Write Strobe for Interrupt Flag Register 2
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wire [1:0] write_xgif_2; // Write Strobe for Interrupt Flag Register 2
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wire [1:0] write_xgif_1; // Write Strobe for Interrupt Flag Register 1
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wire [1:0] write_xgif_1; // Write Strobe for Interrupt Flag Register 1
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wire [1:0] write_xgif_0; // Write Strobe for Interrupt Flag Register 0
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wire [1:0] write_xgif_0; // Write Strobe for Interrupt Flag Register 0
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wire [1:0] write_irw_en_7; // Write Strobe for Interrupt Bypass Control Register 7
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wire [1:0] write_irw_en_6; // Write Strobe for Interrupt Bypass Control Register 6
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wire [1:0] write_irw_en_5; // Write Strobe for Interrupt Bypass Control Register 5
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wire [1:0] write_irw_en_4; // Write Strobe for Interrupt Bypass Control Register 4
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wire [1:0] write_irw_en_3; // Write Strobe for Interrupt Bypass Control Register 3
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wire [1:0] write_irw_en_2; // Write Strobe for Interrupt Bypass Control Register 2
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wire [1:0] write_irw_en_1; // Write Strobe for Interrupt Bypass Control Register 1
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wire [1:0] write_irw_en_0; // Write Strobe for Interrupt Bypass Control Register 0
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wire write_xgswt; // Write Strobe for XGSWT register
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wire write_xgswt; // Write Strobe for XGSWT register
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wire write_xgsem; // Write Strobe for XGSEM register
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wire write_xgsem; // Write Strobe for XGSEM register
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wire write_xgccr; // Write Strobe for XGATE Condition Code Register
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wire write_xgccr; // Write Strobe for XGATE Condition Code Register
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wire [1:0] write_xgpc; // Write Strobe for XGATE Program Counter
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wire [1:0] write_xgpc; // Write Strobe for XGATE Program Counter
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wire [1:0] write_xgr7; // Write Strobe for XGATE Data Register R7
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wire [1:0] write_xgr7; // Write Strobe for XGATE Data Register R7
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Line 128... |
wire clear_xgif_3; // Strobe for decode to clear interrupt flag bank 3
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wire clear_xgif_3; // Strobe for decode to clear interrupt flag bank 3
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wire clear_xgif_2; // Strobe for decode to clear interrupt flag bank 2
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wire clear_xgif_2; // Strobe for decode to clear interrupt flag bank 2
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wire clear_xgif_1; // Strobe for decode to clear interrupt flag bank 1
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wire clear_xgif_1; // Strobe for decode to clear interrupt flag bank 1
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wire clear_xgif_0; // Strobe for decode to clear interrupt flag bank 0
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wire clear_xgif_0; // Strobe for decode to clear interrupt flag bank 0
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wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag
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wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag
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wire [MAX_CHANNEL:0] chan_bypass; // XGATE Interrupt enable or bypass
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wire xge; // XGATE Module Enable
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wire xge; // XGATE Module Enable
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wire xgfrz; // Stop XGATE in Freeze Mode
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wire xgfrz; // Stop XGATE in Freeze Mode
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wire xgdbg_set; // Enter XGATE Debug Mode
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wire xgdbg_set; // Enter XGATE Debug Mode
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wire xgdbg_clear; // Leave XGATE Debug Mode
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wire xgdbg_clear; // Leave XGATE Debug Mode
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wire xgsweif_c; // Clear XGATE Software Error Interrupt FLag
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wire xgsweif_c; // Clear XGATE Software Error Interrupt FLag
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wire xgie; // XGATE Interrupt Enable
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wire xgie; // XGATE Interrupt Enable
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wire [ 6:0] int_req; // Encoded interrupt request
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wire [ 6:0] int_req; // Encoded interrupt request
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wire [ 6:0] xgchid; // Channel actively being processed
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wire [ 6:0] xgchid; // Channel actively being processed
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wire [127:0] xgif_status; // Status bits of interrupt output flags that have been set
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wire [127:0] xgif_status; // Status bits of interrupt output flags that have been set
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wire [127:0] irq_bypass; // IRQ status bits WISHBONE Read bus
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wire [15:1] xgvbr; // XGATE vector Base Address Register
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wire [15:1] xgvbr; // XGATE vector Base Address Register
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wire brk_irq_ena; // Enable BRK instruction to generate interrupt
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wire brk_irq_ena; // Enable BRK instruction to generate interrupt
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wire [15:0] xgate_address; //
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wire [15:0] xgate_address; //
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wire [15:0] write_mem_data; //
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wire [15:0] write_mem_data; //
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Line 161... |
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wire [ 7:0] host_semap; // Semaphore status for host
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wire [ 7:0] host_semap; // Semaphore status for host
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wire write_mem_strb_l; // Strobe for writing low data byte
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wire write_mem_strb_l; // Strobe for writing low data byte
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wire write_mem_strb_h; // Strobe for writing high data bye
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wire write_mem_strb_h; // Strobe for writing high data bye
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assign xgif = xgif_status[MAX_CHANNEL:0];
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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// Wishbone Slave Bus interface
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// Wishbone Slave Bus interface
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xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
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xgate_wbs_bus #(.ARST_LVL(ARST_LVL),
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.SINGLE_CYCLE(SINGLE_CYCLE))
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.SINGLE_CYCLE(SINGLE_CYCLE),
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.WB_RD_DEFAULT(WB_RD_DEFAULT))
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wishbone_s(
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wishbone_s(
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.wbs_dat_o( wbs_dat_o ),
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.wbs_dat_o( wbs_dat_o ),
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.wbs_ack_o( wbs_ack_o ),
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.wbs_ack_o( wbs_ack_o ),
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.wbs_err_o( wbs_err_o ),
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.wbs_err_o( wbs_err_o ),
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.wbs_clk_i( wbs_clk_i ),
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.wbs_clk_i( wbs_clk_i ),
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Line 204... |
.write_xgr5( write_xgr5 ),
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.write_xgr5( write_xgr5 ),
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.write_xgr4( write_xgr4 ),
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.write_xgr4( write_xgr4 ),
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.write_xgr3( write_xgr3 ),
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.write_xgr3( write_xgr3 ),
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.write_xgr2( write_xgr2 ),
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.write_xgr2( write_xgr2 ),
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.write_xgr1( write_xgr1 ),
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.write_xgr1( write_xgr1 ),
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.write_irw_en_7( write_irw_en_7 ),
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.write_irw_en_6( write_irw_en_6 ),
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.write_irw_en_5( write_irw_en_5 ),
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.write_irw_en_4( write_irw_en_4 ),
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.write_irw_en_3( write_irw_en_3 ),
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.write_irw_en_2( write_irw_en_2 ),
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.write_irw_en_1( write_irw_en_1 ),
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.write_irw_en_0( write_irw_en_0 ),
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// inputs
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// inputs
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.async_rst_b ( async_rst_b ),
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.async_rst_b ( async_rst_b ),
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.read_regs ( // in -- read register bits
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.read_risc_regs( // in -- read register bits
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{ xgr7, // XGR7
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{ xgr7, // XGR7
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xgr6, // XGR6
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xgr6, // XGR6
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xgr5, // XGR5
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xgr5, // XGR5
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xgr4, // XGR4
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xgr4, // XGR4
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xgr3, // XGR3
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xgr3, // XGR3
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Line 242... |
16'b0, // Reserved
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16'b0, // Reserved
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16'b0, // Reserved
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16'b0, // Reserved
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{8'b0, 1'b0, xgchid}, // XGCHID
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{8'b0, 1'b0, xgchid}, // XGCHID
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{8'b0, xge, xgfrz, debug_active, 1'b0, xgfact, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL
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{8'b0, xge, xgfrz, debug_active, 1'b0, xgfact, brk_irq_ena, xg_sw_irq, xgie} // XGMCTL
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}
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}
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)
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),
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.irq_bypass( irq_bypass )
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);
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);
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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xgate_regs #(.ARST_LVL(ARST_LVL),
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xgate_regs #(.ARST_LVL(ARST_LVL),
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.MAX_CHANNEL(MAX_CHANNEL))
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.MAX_CHANNEL(MAX_CHANNEL))
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Line 272... |
.clear_xgif_3( clear_xgif_3 ),
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.clear_xgif_3( clear_xgif_3 ),
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.clear_xgif_2( clear_xgif_2 ),
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.clear_xgif_2( clear_xgif_2 ),
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.clear_xgif_1( clear_xgif_1 ),
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.clear_xgif_1( clear_xgif_1 ),
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.clear_xgif_0( clear_xgif_0 ),
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.clear_xgif_0( clear_xgif_0 ),
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.clear_xgif_data( clear_xgif_data ),
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.clear_xgif_data( clear_xgif_data ),
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.irq_bypass( irq_bypass ),
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.chan_bypass( chan_bypass ),
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// inputs
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// inputs
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.async_rst_b( async_rst_b ),
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.async_rst_b( async_rst_b ),
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.sync_reset( sync_reset ),
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.sync_reset( sync_reset ),
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.bus_clk( wbs_clk_i ),
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.bus_clk( wbs_clk_i ),
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Line 290... |
.write_xgif_4( write_xgif_4 ),
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.write_xgif_4( write_xgif_4 ),
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.write_xgif_3( write_xgif_3 ),
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.write_xgif_3( write_xgif_3 ),
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.write_xgif_2( write_xgif_2 ),
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.write_xgif_2( write_xgif_2 ),
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.write_xgif_1( write_xgif_1 ),
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.write_xgif_1( write_xgif_1 ),
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.write_xgif_0( write_xgif_0 ),
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.write_xgif_0( write_xgif_0 ),
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.write_irw_en_7( write_irw_en_7 ),
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.write_irw_en_6( write_irw_en_6 ),
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.write_irw_en_5( write_irw_en_5 ),
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.write_irw_en_4( write_irw_en_4 ),
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.write_irw_en_3( write_irw_en_3 ),
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.write_irw_en_2( write_irw_en_2 ),
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.write_irw_en_1( write_irw_en_1 ),
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.write_irw_en_0( write_irw_en_0 ),
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.write_xgswt( write_xgswt ),
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.write_xgswt( write_xgswt ),
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.debug_ack( debug_ack )
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.debug_ack( debug_ack )
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);
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);
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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| Line 339... |
Line 372... |
);
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);
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xgate_irq_encode #(.MAX_CHANNEL(MAX_CHANNEL))
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xgate_irq_encode #(.MAX_CHANNEL(MAX_CHANNEL))
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irq_encode(
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irq_encode(
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// outputs
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// outputs
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.xgif( xgif ),
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.int_req( int_req ),
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.int_req( int_req ),
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// inputs
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// inputs
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.chan_req_i( chan_req_i )
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.chan_req_i( chan_req_i ),
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.chan_bypass( chan_bypass ),
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.xgif_status( xgif_status )
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);
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);
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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// Wishbone Master Bus interface
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// Wishbone Master Bus interface
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xgate_wbm_bus #(.ARST_LVL(ARST_LVL))
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xgate_wbm_bus #(.ARST_LVL(ARST_LVL))
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