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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_top.v] - Diff between revs 67 and 72

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Rev 67 Rev 72
Line 66... Line 66...
  input     [DWIDTH-1:0] wbm_dat_i,     // databus input
  input     [DWIDTH-1:0] wbm_dat_i,     // databus input
  input                  wbm_ack_i,     // bus cycle acknowledge input
  input                  wbm_ack_i,     // bus cycle acknowledge input
  // XGATE IO Signals
  // XGATE IO Signals
  output          [ 7:0] xgswt,         // XGATE Software Trigger Register
  output          [ 7:0] xgswt,         // XGATE Software Trigger Register
  output                 xg_sw_irq,        // Xgate Software interrupt
  output                 xg_sw_irq,        // Xgate Software interrupt
  output [MAX_CHANNEL:0] xgif,             // XGATE Interrupt Flag to Host
  output [MAX_CHANNEL:1] xgif,             // XGATE Interrupt Flag to Host
  input  [MAX_CHANNEL:0] chan_req_i,       // XGATE Interrupt request
  input  [MAX_CHANNEL:1] chan_req_i,       // XGATE Interrupt request
  input                  risc_clk,         // Clock for RISC core
  input                  risc_clk,         // Clock for RISC core
  input                  debug_mode_i,     // Force RISC core into debug mode
  input                  debug_mode_i,     // Force RISC core into debug mode
  input                  secure_mode_i,    // Limit host asscess to Xgate RISC registers
  input                  secure_mode_i,    // Limit host asscess to Xgate RISC registers
  input                  scantestmode      // Chip in in scan test mode
  input                  scantestmode      // Chip in in scan test mode
  );
  );
Line 128... Line 128...
  wire        clear_xgif_3;    // Strobe for decode to clear interrupt flag bank 3
  wire        clear_xgif_3;    // Strobe for decode to clear interrupt flag bank 3
  wire        clear_xgif_2;    // Strobe for decode to clear interrupt flag bank 2
  wire        clear_xgif_2;    // Strobe for decode to clear interrupt flag bank 2
  wire        clear_xgif_1;    // Strobe for decode to clear interrupt flag bank 1
  wire        clear_xgif_1;    // Strobe for decode to clear interrupt flag bank 1
  wire        clear_xgif_0;    // Strobe for decode to clear interrupt flag bank 0
  wire        clear_xgif_0;    // Strobe for decode to clear interrupt flag bank 0
  wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag
  wire [15:0] clear_xgif_data; // Data for decode to clear interrupt flag
  wire [MAX_CHANNEL:0] chan_bypass; // XGATE Interrupt enable or bypass
  wire [MAX_CHANNEL:1] chan_bypass; // XGATE Interrupt enable or bypass
 
 
  wire        xge;           // XGATE Module Enable
  wire        xge;           // XGATE Module Enable
  wire        xgfrz;         // Stop XGATE in Freeze Mode
  wire        xgfrz;         // Stop XGATE in Freeze Mode
  wire        xgdbg_set;     // Enter XGATE Debug Mode
  wire        xgdbg_set;     // Enter XGATE Debug Mode
  wire        xgdbg_clear;   // Leave XGATE Debug Mode
  wire        xgdbg_clear;   // Leave XGATE Debug Mode
Line 140... Line 140...
  wire        xgss;          // XGATE Single Step
  wire        xgss;          // XGATE Single Step
  wire        xgsweif_c;     // Clear XGATE Software Error Interrupt FLag
  wire        xgsweif_c;     // Clear XGATE Software Error Interrupt FLag
  wire        xgie;          // XGATE Interrupt Enable
  wire        xgie;          // XGATE Interrupt Enable
  wire [ 6:0] int_req;       // Encoded interrupt request
  wire [ 6:0] int_req;       // Encoded interrupt request
  wire [ 6:0] xgchid;        // Channel actively being processed
  wire [ 6:0] xgchid;        // Channel actively being processed
  wire [127:0] xgif_status;  // Status bits of interrupt output flags that have been set
  wire [127:1] xgif_status;  // Status bits of interrupt output flags that have been set
  wire [127:0] irq_bypass;   // IRQ status bits WISHBONE Read bus
  wire [127:1] irq_bypass;   // IRQ status bits WISHBONE Read bus
 
 
  wire [15:1] xgvbr;         // XGATE vector Base Address Register
  wire [15:1] xgvbr;         // XGATE vector Base Address Register
  wire        brk_irq_ena;   // Enable BRK instruction to generate interrupt
  wire        brk_irq_ena;   // Enable BRK instruction to generate interrupt
 
 
  wire [15:0] xgate_address;   //
  wire [15:0] xgate_address;   //
Line 228... Line 228...
                     xgate_address,    // XGPC
                     xgate_address,    // XGPC
                     {12'h000,  negative_flag, zero_flag, overflow_flag, carry_flag},  // XGCCR
                     {12'h000,  negative_flag, zero_flag, overflow_flag, carry_flag},  // XGCCR
                     16'b0,                // Reserved
                     16'b0,                // Reserved
                     {8'h00, host_semap},  // XGSEM
                     {8'h00, host_semap},  // XGSEM
                     {8'h00, xgswt},       // XGSWT
                     {8'h00, xgswt},       // XGSWT
                     xgif_status[ 15:  0], // XGIF_0
                     {xgif_status[ 15:  1], 1'b0}, // XGIF_0
                     xgif_status[ 31: 16], // XGIF_1
                     xgif_status[ 31: 16], // XGIF_1
                     xgif_status[ 47: 32], // XGIF_2
                     xgif_status[ 47: 32], // XGIF_2
                     xgif_status[ 63: 48], // XGIF_3
                     xgif_status[ 63: 48], // XGIF_3
                     xgif_status[ 79: 64], // XGIF_4
                     xgif_status[ 79: 64], // XGIF_4
                     xgif_status[ 95: 80], // XGIF_5
                     xgif_status[ 95: 80], // XGIF_5

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