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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module xgate_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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module xgate_top #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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parameter DWIDTH = 16, // define the wishbone bus data size
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parameter SINGLE_CYCLE = 1'b0, //
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parameter SINGLE_CYCLE = 1'b0, //
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parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
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parameter MAX_CHANNEL = 127, // Max XGATE Interrupt Channel Number
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parameter WB_RD_DEFAULT = 0) // WISHBONE Read Bus default state
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parameter WB_RD_DEFAULT = 0) // WISHBONE Read Bus default state
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(
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(
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// Wishbone Slave Signals
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// Wishbone Slave Signals
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input debug_mode_i, // Force RISC core into debug mode
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input debug_mode_i, // Force RISC core into debug mode
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input secure_mode_i, // Limit host asscess to Xgate RISC registers
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input secure_mode_i, // Limit host asscess to Xgate RISC registers
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input scantestmode // Chip in in scan test mode
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input scantestmode // Chip in in scan test mode
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);
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);
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parameter DWIDTH = 16; // Data bus width
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wire zero_flag;
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wire zero_flag;
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wire negative_flag;
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wire negative_flag;
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wire carry_flag;
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wire carry_flag;
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wire overflow_flag;
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wire overflow_flag;
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