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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbm_bus.v] - Diff between revs 12 and 29
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Rev 29 |
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Line 79... |
assign read_mem_data = wbm_dat_i;
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assign read_mem_data = wbm_dat_i;
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assign wbm_adr_o = xgate_address;
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assign wbm_adr_o = xgate_address;
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assign mem_req_ack = wbm_ack_i;
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assign mem_req_ack = wbm_ack_i;
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assign wbm_we_o = write_mem_strb_h || write_mem_strb_l;
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assign wbm_sel_o = {write_mem_strb_h, write_mem_strb_l};
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assign wbm_cyc_o = 1'b1;
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assign wbm_stb_o = 1'b1;
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endmodule // xgate_wbm_bus
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endmodule // xgate_wbm_bus
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