URL
https://opencores.org/ocsvn/xgate/xgate/trunk
[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbm_bus.v] - Diff between revs 12 and 29
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 12 |
Rev 29 |
| Line 79... |
Line 79... |
assign read_mem_data = wbm_dat_i;
|
assign read_mem_data = wbm_dat_i;
|
assign wbm_adr_o = xgate_address;
|
assign wbm_adr_o = xgate_address;
|
|
|
assign mem_req_ack = wbm_ack_i;
|
assign mem_req_ack = wbm_ack_i;
|
|
|
|
assign wbm_we_o = write_mem_strb_h || write_mem_strb_l;
|
|
|
|
assign wbm_sel_o = {write_mem_strb_h, write_mem_strb_l};
|
|
|
|
assign wbm_cyc_o = 1'b1;
|
|
|
|
assign wbm_stb_o = 1'b1;
|
|
|
endmodule // xgate_wbm_bus
|
endmodule // xgate_wbm_bus
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
