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input wbs_rst_i, // synchronous active high reset
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input wbs_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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input arst_i, // asynchronous reset
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// XGATE Control Signals
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// XGATE Control Signals
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output [DWIDTH-1:0] read_mem_data, // Data from system memory
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output [DWIDTH-1:0] read_mem_data, // Data from system memory
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output mem_req_ack, // Memory bus transaction complete
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output mem_req_ack, // Memory bus transaction complete
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input xge, // XGATE Enabled
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input [15:0] xgate_address, // Address to system memory
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input [15:0] xgate_address, // Address to system memory
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input mem_access, //
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input write_mem_strb_l, // Strobe for writing low data byte
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input write_mem_strb_l, // Strobe for writing low data byte
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input write_mem_strb_h, // Strobe for writing high data bye
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input write_mem_strb_h, // Strobe for writing high data bye
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input [DWIDTH-1:0] write_mem_data // Data to system memory
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input [DWIDTH-1:0] write_mem_data // Data to system memory
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);
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);
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// registers
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// Wires and Registers
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// Wires
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wire module_sel; // This module is selected for bus transaction
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wire module_sel; // This module is selected for bus transaction
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//
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//
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// module body
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// Module body
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//
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//
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// generate internal resets
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assign wbm_dat_o = write_mem_data;
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assign wbm_dat_o = write_mem_data;
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assign read_mem_data = wbm_dat_i;
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assign read_mem_data = wbm_dat_i;
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assign wbm_adr_o = xgate_address;
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assign wbm_adr_o = xgate_address;
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assign mem_req_ack = wbm_ack_i;
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assign mem_req_ack = wbm_ack_i;
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assign wbm_we_o = write_mem_strb_h || write_mem_strb_l;
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assign wbm_we_o = write_mem_strb_h || write_mem_strb_l;
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assign wbm_sel_o = {write_mem_strb_h, write_mem_strb_l};
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assign wbm_sel_o = {write_mem_strb_h, write_mem_strb_l};
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assign wbm_cyc_o = 1'b1;
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assign wbm_cyc_o = xge && mem_access;
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assign wbm_stb_o = 1'b1;
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assign wbm_stb_o = xge && mem_access;
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endmodule // xgate_wbm_bus
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endmodule // xgate_wbm_bus
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