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input wbs_rst_i, // synchronous active high reset
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input wbs_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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input arst_i, // asynchronous reset
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// XGATE Control Signals
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// XGATE Control Signals
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output [DWIDTH-1:0] read_mem_data, // Data from system memory
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output [DWIDTH-1:0] read_mem_data, // Data from system memory
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output mem_req_ack, // Memory bus transaction complete
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output mem_req_ack, // Memory bus transaction complete
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input risc_clk, //
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input async_rst_b, //
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input xge, // XGATE Enabled
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input xge, // XGATE Enabled
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input single_step, // Pulse to trigger a single instruction execution in debug mode
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output ss_mem_ack, // WISHBONE Bus has granted single step memory access
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input [15:0] xgate_address, // Address to system memory
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input [15:0] xgate_address, // Address to system memory
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input mem_access, //
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input mem_access, //
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input write_mem_strb_l, // Strobe for writing low data byte
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input write_mem_strb_l, // Strobe for writing low data byte
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input write_mem_strb_h, // Strobe for writing high data bye
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input write_mem_strb_h, // Strobe for writing high data bye
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input [DWIDTH-1:0] write_mem_data // Data to system memory
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input [DWIDTH-1:0] write_mem_data // Data to system memory
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);
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);
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// Wires and Registers
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// Wires and Registers
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wire module_sel; // This module is selected for bus transaction
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wire module_sel; // This module is selected for bus transaction
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reg ss_mem_req; // Bus request for single step memory access
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//
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//
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// Module body
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// Module body
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//
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//
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// Latch Single Step Request and ask for memory access
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always @(posedge risc_clk or negedge async_rst_b)
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if ( !async_rst_b )
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ss_mem_req <= 1'b0;
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else
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ss_mem_req <= (single_step || ss_mem_req) && !wbm_ack_i && xge;
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assign ss_mem_ack = ss_mem_req && wbm_ack_i;
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assign wbm_dat_o = write_mem_data;
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assign wbm_dat_o = write_mem_data;
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assign read_mem_data = wbm_dat_i;
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assign read_mem_data = wbm_dat_i;
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assign wbm_adr_o = xgate_address;
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assign wbm_adr_o = xgate_address;
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assign mem_req_ack = wbm_ack_i;
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assign mem_req_ack = wbm_ack_i;
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assign wbm_we_o = write_mem_strb_h || write_mem_strb_l;
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assign wbm_we_o = write_mem_strb_h || write_mem_strb_l;
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assign wbm_sel_o = {write_mem_strb_h, write_mem_strb_l};
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assign wbm_sel_o = {write_mem_strb_h, write_mem_strb_l};
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assign wbm_cyc_o = xge && mem_access;
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assign wbm_cyc_o = xge && (mem_access || ss_mem_req);
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assign wbm_stb_o = xge && mem_access;
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assign wbm_stb_o = xge && (mem_access || ss_mem_req);
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endmodule // xgate_wbm_bus
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endmodule // xgate_wbm_bus
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