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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbm_bus.v] - Diff between revs 89 and 96
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| Rev 89 |
Rev 96 |
| Line 49... |
Line 49... |
output wbm_cyc_o, // valid bus cycle output
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output wbm_cyc_o, // valid bus cycle output
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output [ 1:0] wbm_sel_o, // Select byte in word bus transaction
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output [ 1:0] wbm_sel_o, // Select byte in word bus transaction
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output [15:0] wbm_adr_o, // Address bits
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output [15:0] wbm_adr_o, // Address bits
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input [DWIDTH-1:0] wbm_dat_i, // databus input
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input [DWIDTH-1:0] wbm_dat_i, // databus input
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input wbm_ack_i, // bus cycle acknowledge input
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input wbm_ack_i, // bus cycle acknowledge input
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input wbs_clk_i, // master clock input
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input wbs_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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// XGATE Control Signals
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// XGATE Control Signals
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output [DWIDTH-1:0] read_mem_data, // Data from system memory
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output [DWIDTH-1:0] read_mem_data, // Data from system memory
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output mem_req_ack, // Memory bus transaction complete
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output mem_req_ack, // Memory bus transaction complete
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input risc_clk, //
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input risc_clk, //
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input async_rst_b, //
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input async_rst_b, //
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