| Line 54... |
Line 54... |
input wbs_stb_i, // stobe/core select signal
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input wbs_stb_i, // stobe/core select signal
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input wbs_cyc_i, // valid bus cycle input
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input wbs_cyc_i, // valid bus cycle input
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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// XGATE Control Signals
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// XGATE Control Signals
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output reg write_xgmctl, // Write Strobe for XGMCTL register
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output reg write_xgmctl, // Write Strobe for XGMCTL register
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output reg write_xgchid, // Write Strobe for XGCHID register
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output reg write_xgisp74,// Write Strobe for XGISP74 register
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output reg write_xgisp74,// Write Strobe for XGISP74 register
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output reg write_xgisp30,// Write Strobe for XGISP30 register
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output reg write_xgisp30,// Write Strobe for XGISP30 register
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output reg write_xgvbr, // Write Strobe for XGVBR register
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output reg write_xgvbr, // Write Strobe for XGVBR register
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output reg write_xgif_7, // Write Strobe for Interrupt Flag Register 7
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output reg write_xgif_7, // Write Strobe for Interrupt Flag Register 7
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output reg write_xgif_6, // Write Strobe for Interrupt Flag Register 6
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output reg write_xgif_6, // Write Strobe for Interrupt Flag Register 6
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| Line 87... |
Line 88... |
// registers
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// registers
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reg bus_wait_state; // Holdoff wbs_ack_o for one clock to add wait state
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reg bus_wait_state; // Holdoff wbs_ack_o for one clock to add wait state
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reg [DWIDTH-1:0] rd_data_mux; // Pseudo Register, WISHBONE Read Data Mux
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reg [DWIDTH-1:0] rd_data_mux; // Pseudo Register, WISHBONE Read Data Mux
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reg [DWIDTH-1:0] rd_data_reg; // Latch for WISHBONE Read Data
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reg [DWIDTH-1:0] rd_data_reg; // Latch for WISHBONE Read Data
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reg write_reserv; // Dummy Reg decode for Reserved address
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reg write_reserv1; // Dummy Reg decode for Reserved address
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reg write_reserv2; // Dummy Reg decode for Reserved address
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// Wires
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// Wires
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wire module_sel; // This module is selected for bus transaction
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wire module_sel; // This module is selected for bus transaction
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wire wbs_wacc; // WISHBONE Write Strobe (Clock gating signal)
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wire wbs_wacc; // WISHBONE Write Strobe (Clock gating signal)
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wire wbs_racc; // WISHBONE Read Access (Clock gating signal)
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wire wbs_racc; // WISHBONE Read Access (Clock gating signal)
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| Line 161... |
Line 163... |
endcase
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endcase
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// generate wishbone write register strobes
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// generate wishbone write register strobes
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always @*
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always @*
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begin
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begin
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write_reserv = 1'b0;
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write_reserv1 = 1'b0;
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write_reserv2 = 1'b0;
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write_xgmctl = 1'b0;
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write_xgmctl = 1'b0;
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write_xgchid = 1'b0;
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write_xgisp74 = 1'b0;
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write_xgisp74 = 1'b0;
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write_xgisp30 = 1'b0;
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write_xgisp30 = 1'b0;
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write_xgvbr = 1'b0;
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write_xgvbr = 1'b0;
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write_xgif_7 = 1'b0;
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write_xgif_7 = 1'b0;
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write_xgif_6 = 1'b0;
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write_xgif_6 = 1'b0;
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| Line 190... |
Line 194... |
write_xgr1 = 1'b0;
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write_xgr1 = 1'b0;
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if (wbs_wacc)
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if (wbs_wacc)
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case (wbs_adr_i) // synopsys parallel_case
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case (wbs_adr_i) // synopsys parallel_case
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// 16 bit Bus, 16 bit Granularity
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// 16 bit Bus, 16 bit Granularity
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5'b0_0000 : write_xgmctl = 1'b1;
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5'b0_0000 : write_xgmctl = 1'b1;
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// 5'b0_0001 : write_xgchid = 1'b1;
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5'b0_0001 : write_xgchid = 1'b1;
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5'b0_0010 : write_xgisp74 = 1'b1;
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5'b0_0010 : write_xgisp74 = 1'b1;
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5'b0_0011 : write_xgisp30 = 1'b1;
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5'b0_0011 : write_xgisp30 = 1'b1;
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5'b0_0100 : write_xgvbr = 1'b1;
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5'b0_0100 : write_xgvbr = 1'b1;
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5'b0_0101 : write_xgif_7 = 1'b1;
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5'b0_0101 : write_xgif_7 = 1'b1;
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5'b0_0110 : write_xgif_6 = 1'b1;
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5'b0_0110 : write_xgif_6 = 1'b1;
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| Line 204... |
Line 208... |
5'b0_1010 : write_xgif_2 = 1'b1;
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5'b0_1010 : write_xgif_2 = 1'b1;
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5'b0_1011 : write_xgif_1 = 1'b1;
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5'b0_1011 : write_xgif_1 = 1'b1;
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5'b0_1100 : write_xgif_0 = 1'b1;
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5'b0_1100 : write_xgif_0 = 1'b1;
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5'b0_1101 : write_xgswt = 1'b1;
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5'b0_1101 : write_xgswt = 1'b1;
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5'b0_1110 : write_xgsem = 1'b1;
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5'b0_1110 : write_xgsem = 1'b1;
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5'b0_1111 : write_reserv = 1'b1;
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5'b0_1111 : write_reserv1 = 1'b1;
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5'b1_0000 : write_xgccr = 1'b1;
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5'b1_0000 : write_xgccr = 1'b1;
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5'b1_0001 : write_xgpc = 1'b1;
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5'b1_0001 : write_xgpc = 1'b1;
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5'b1_0010 : write_reserv = 1'b1;
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5'b1_0010 : write_reserv2 = 1'b1;
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5'b1_0011 : write_xgr1 = 1'b1;
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5'b1_0011 : write_xgr1 = 1'b1;
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5'b1_0100 : write_xgr2 = 1'b1;
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5'b1_0100 : write_xgr2 = 1'b1;
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5'b1_0101 : write_xgr3 = 1'b1;
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5'b1_0101 : write_xgr3 = 1'b1;
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5'b1_0110 : write_xgr4 = 1'b1;
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5'b1_0110 : write_xgr4 = 1'b1;
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5'b1_0111 : write_xgr5 = 1'b1;
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5'b1_0111 : write_xgr5 = 1'b1;
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