| Line 46... |
Line 46... |
output [DWIDTH-1:0] wbs_dat_o, // databus output
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output [DWIDTH-1:0] wbs_dat_o, // databus output
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output wbs_ack_o, // bus cycle acknowledge output
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output wbs_ack_o, // bus cycle acknowledge output
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input wbs_clk_i, // master clock input
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input wbs_clk_i, // master clock input
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input wbs_rst_i, // synchronous active high reset
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input wbs_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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input arst_i, // asynchronous reset
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input [ 4:0] wbs_adr_i, // lower address bits
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input [ 5:1] wbs_adr_i, // lower address bits
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input wbs_we_i, // write enable input
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input wbs_we_i, // write enable input
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input wbs_stb_i, // stobe/core select signal
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input wbs_stb_i, // stobe/core select signal
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input wbs_cyc_i, // valid bus cycle input
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input wbs_cyc_i, // valid bus cycle input
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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// XGATE Control Signals
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// XGATE Control Signals
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output reg write_xgmctl, // Write Strobe for XGMCTL register
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output reg write_xgmctl, // Write Strobe for XGMCTL register
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output reg write_xgchid, // Write Strobe for XGCHID register
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output reg write_xgchid, // Write Strobe for XGCHID register
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output reg write_xgisp74,// Write Strobe for XGISP74 register
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output reg write_xgisp74,// Write Strobe for XGISP74 register
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output reg write_xgisp30,// Write Strobe for XGISP30 register
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output reg write_xgisp30,// Write Strobe for XGISP30 register
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output reg write_xgvbr, // Write Strobe for XGVBR register
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output reg [1:0] write_xgvbr, // Write Strobe for XGVBR register
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output reg write_xgif_7, // Write Strobe for Interrupt Flag Register 7
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output reg [1:0] write_xgif_7, // Write Strobe for Interrupt Flag Register 7
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output reg write_xgif_6, // Write Strobe for Interrupt Flag Register 6
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output reg [1:0] write_xgif_6, // Write Strobe for Interrupt Flag Register 6
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output reg write_xgif_5, // Write Strobe for Interrupt Flag Register 5
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output reg [1:0] write_xgif_5, // Write Strobe for Interrupt Flag Register 5
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output reg write_xgif_4, // Write Strobe for Interrupt Flag Register 4
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output reg [1:0] write_xgif_4, // Write Strobe for Interrupt Flag Register 4
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output reg write_xgif_3, // Write Strobe for Interrupt Flag Register 3
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output reg [1:0] write_xgif_3, // Write Strobe for Interrupt Flag Register 3
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output reg write_xgif_2, // Write Strobe for Interrupt Flag Register 2
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output reg [1:0] write_xgif_2, // Write Strobe for Interrupt Flag Register 2
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output reg write_xgif_1, // Write Strobe for Interrupt Flag Register 1
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output reg [1:0] write_xgif_1, // Write Strobe for Interrupt Flag Register 1
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output reg write_xgif_0, // Write Strobe for Interrupt Flag Register 0
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output reg [1:0] write_xgif_0, // Write Strobe for Interrupt Flag Register 0
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output reg write_xgswt, // Write Strobe for XGSWT register
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output reg write_xgswt, // Write Strobe for XGSWT register
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output reg write_xgsem, // Write Strobe for XGSEM register
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output reg write_xgsem, // Write Strobe for XGSEM register
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output reg write_xgccr, // Write Strobe for XGATE Condition Code Register
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output reg write_xgccr, // Write Strobe for XGATE Condition Code Register
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output reg write_xgpc, // Write Strobe for XGATE Program Counter
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output reg [1:0] write_xgpc, // Write Strobe for XGATE Program Counter
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output reg write_xgr7, // Write Strobe for XGATE Data Register R7
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output reg [1:0] write_xgr7, // Write Strobe for XGATE Data Register R7
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output reg write_xgr6, // Write Strobe for XGATE Data Register R6
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output reg [1:0] write_xgr6, // Write Strobe for XGATE Data Register R6
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output reg write_xgr5, // Write Strobe for XGATE Data Register R5
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output reg [1:0] write_xgr5, // Write Strobe for XGATE Data Register R5
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output reg write_xgr4, // Write Strobe for XGATE Data Register R4
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output reg [1:0] write_xgr4, // Write Strobe for XGATE Data Register R4
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output reg write_xgr3, // Write Strobe for XGATE Data Register R3
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output reg [1:0] write_xgr3, // Write Strobe for XGATE Data Register R3
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output reg write_xgr2, // Write Strobe for XGATE Data Register R2
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output reg [1:0] write_xgr2, // Write Strobe for XGATE Data Register R2
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output reg write_xgr1, // Write Strobe for XGATE Data Register R1
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output reg [1:0] write_xgr1, // Write Strobe for XGATE Data Register R1
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output async_rst_b, //
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output async_rst_b, //
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output sync_reset, //
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output sync_reset, //
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input [415:0] read_regs // status register bits
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input [415:0] read_regs // status register bits
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);
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);
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| Line 169... |
Line 169... |
write_reserv2 = 1'b0;
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write_reserv2 = 1'b0;
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write_xgmctl = 1'b0;
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write_xgmctl = 1'b0;
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write_xgchid = 1'b0;
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write_xgchid = 1'b0;
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write_xgisp74 = 1'b0;
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write_xgisp74 = 1'b0;
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write_xgisp30 = 1'b0;
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write_xgisp30 = 1'b0;
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write_xgvbr = 1'b0;
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write_xgvbr = 2'b00;
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write_xgif_7 = 1'b0;
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write_xgif_7 = 2'b00;
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write_xgif_6 = 1'b0;
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write_xgif_6 = 2'b00;
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write_xgif_5 = 1'b0;
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write_xgif_5 = 2'b00;
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write_xgif_4 = 1'b0;
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write_xgif_4 = 2'b00;
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write_xgif_3 = 1'b0;
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write_xgif_3 = 2'b00;
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write_xgif_2 = 1'b0;
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write_xgif_2 = 2'b00;
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write_xgif_1 = 1'b0;
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write_xgif_1 = 2'b00;
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write_xgif_0 = 1'b0;
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write_xgif_0 = 2'b00;
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write_xgif_7 = 1'b0;
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write_xgswt = 1'b0;
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write_xgswt = 1'b0;
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write_xgsem = 1'b0;
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write_xgsem = 1'b0;
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write_xgccr = 1'b0;
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write_xgccr = 1'b0;
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write_xgpc = 1'b0;
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write_xgpc = 2'b00;
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write_xgr7 = 1'b0;
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write_xgr7 = 2'b00;
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write_xgr6 = 1'b0;
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write_xgr6 = 2'b00;
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write_xgr5 = 1'b0;
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write_xgr5 = 2'b00;
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write_xgr4 = 1'b0;
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write_xgr4 = 2'b00;
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write_xgr3 = 1'b0;
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write_xgr3 = 2'b00;
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write_xgr2 = 1'b0;
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write_xgr2 = 2'b00;
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write_xgr1 = 1'b0;
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write_xgr1 = 2'b00;
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if (wbs_wacc)
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if (wbs_wacc)
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case (wbs_adr_i) // synopsys parallel_case
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case (wbs_adr_i) // synopsys parallel_case
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// 16 bit Bus, 16 bit Granularity
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// 16 bit Bus, 8 bit Granularity
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5'b0_0000 : write_xgmctl = 1'b1;
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5'b0_0000 : write_xgmctl = &wbs_sel_i;
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5'b0_0001 : write_xgchid = 1'b1;
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5'b0_0001 : write_xgchid = wbs_sel_i[0];
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5'b0_0010 : write_xgisp74 = 1'b1;
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5'b0_0010 : write_xgisp74 = 1'b1;
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5'b0_0011 : write_xgisp30 = 1'b1;
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5'b0_0011 : write_xgisp30 = 1'b1;
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5'b0_0100 : write_xgvbr = 1'b1;
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5'b0_0100 : write_xgvbr = wbs_sel_i;
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5'b0_0101 : write_xgif_7 = 1'b1;
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5'b0_0101 : write_xgif_7 = wbs_sel_i;
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5'b0_0110 : write_xgif_6 = 1'b1;
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5'b0_0110 : write_xgif_6 = wbs_sel_i;
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5'b0_0111 : write_xgif_5 = 1'b1;
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5'b0_0111 : write_xgif_5 = wbs_sel_i;
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5'b0_1000 : write_xgif_4 = 1'b1;
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5'b0_1000 : write_xgif_4 = wbs_sel_i;
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5'b0_1001 : write_xgif_3 = 1'b1;
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5'b0_1001 : write_xgif_3 = wbs_sel_i;
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5'b0_1010 : write_xgif_2 = 1'b1;
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5'b0_1010 : write_xgif_2 = wbs_sel_i;
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5'b0_1011 : write_xgif_1 = 1'b1;
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5'b0_1011 : write_xgif_1 = wbs_sel_i;
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5'b0_1100 : write_xgif_0 = 1'b1;
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5'b0_1100 : write_xgif_0 = wbs_sel_i;
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5'b0_1101 : write_xgswt = 1'b1;
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5'b0_1101 : write_xgswt = &wbs_sel_i;
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5'b0_1110 : write_xgsem = 1'b1;
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5'b0_1110 : write_xgsem = &wbs_sel_i;
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5'b0_1111 : write_reserv1 = 1'b1;
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5'b0_1111 : write_reserv1 = 1'b1;
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5'b1_0000 : write_xgccr = 1'b1;
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5'b1_0000 : write_xgccr = wbs_sel_i[0];
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5'b1_0001 : write_xgpc = 1'b1;
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5'b1_0001 : write_xgpc = wbs_sel_i;
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5'b1_0010 : write_reserv2 = 1'b1;
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5'b1_0010 : write_reserv2 = 1'b1;
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5'b1_0011 : write_xgr1 = 1'b1;
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5'b1_0011 : write_xgr1 = wbs_sel_i;
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5'b1_0100 : write_xgr2 = 1'b1;
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5'b1_0100 : write_xgr2 = wbs_sel_i;
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5'b1_0101 : write_xgr3 = 1'b1;
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5'b1_0101 : write_xgr3 = wbs_sel_i;
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5'b1_0110 : write_xgr4 = 1'b1;
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5'b1_0110 : write_xgr4 = wbs_sel_i;
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5'b1_0111 : write_xgr5 = 1'b1;
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5'b1_0111 : write_xgr5 = wbs_sel_i;
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5'b1_1000 : write_xgr6 = 1'b1;
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5'b1_1000 : write_xgr6 = wbs_sel_i;
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5'b1_1001 : write_xgr7 = 1'b1;
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5'b1_1001 : write_xgr7 = wbs_sel_i;
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default: ;
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default: ;
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endcase
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endcase
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end
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end
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endmodule // xgate_wbs_bus
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endmodule // xgate_wbs_bus
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