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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbs_bus.v] - Diff between revs 2 and 5
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| Rev 2 |
Rev 5 |
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Line 52... |
input [DWIDTH-1:0] wbs_dat_i, // databus input
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input wbs_we_i, // write enable input
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input wbs_we_i, // write enable input
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input wbs_stb_i, // stobe/core select signal
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input wbs_stb_i, // stobe/core select signal
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input wbs_cyc_i, // valid bus cycle input
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input wbs_cyc_i, // valid bus cycle input
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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// COP Control Signals
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// XGATE Control Signals
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output reg write_xgmctl, // Write Strobe for XGMCTL register
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output reg write_xgmctl, // Write Strobe for XGMCTL register
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output reg write_xgisp74,// Write Strobe for XGISP74 register
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output reg write_xgisp74,// Write Strobe for XGISP74 register
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output reg write_xgisp30,// Write Strobe for XGISP30 register
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output reg write_xgisp30,// Write Strobe for XGISP30 register
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output reg write_xgvbr, // Write Strobe for XGVBR register
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output reg write_xgvbr, // Write Strobe for XGVBR register
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output reg write_xgif_7, // Write Strobe for Interrupt Flag Register 7
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output reg write_xgif_7, // Write Strobe for Interrupt Flag Register 7
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