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parameter SINGLE_CYCLE = 1'b0)
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parameter SINGLE_CYCLE = 1'b0)
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(
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(
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// Wishbone Signals
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// Wishbone Signals
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output [DWIDTH-1:0] wbs_dat_o, // databus output
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output [DWIDTH-1:0] wbs_dat_o, // databus output
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output wbs_ack_o, // bus cycle acknowledge output
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output wbs_ack_o, // bus cycle acknowledge output
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output wbs_err_o, // bus error, lost module select durning wait state
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input wbs_clk_i, // master clock input
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input wbs_clk_i, // master clock input
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input wbs_rst_i, // synchronous active high reset
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input wbs_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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input arst_i, // asynchronous reset
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input [ 5:1] wbs_adr_i, // lower address bits
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input [ 5:1] wbs_adr_i, // lower address bits
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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// generate wishbone signals
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// generate wishbone signals
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assign module_sel = wbs_cyc_i && wbs_stb_i;
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assign module_sel = wbs_cyc_i && wbs_stb_i;
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assign wbs_wacc = module_sel && wbs_we_i && (wbs_ack_o || SINGLE_CYCLE);
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assign wbs_wacc = module_sel && wbs_we_i && (wbs_ack_o || SINGLE_CYCLE);
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assign wbs_racc = module_sel && !wbs_we_i;
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assign wbs_racc = module_sel && !wbs_we_i;
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assign wbs_ack_o = SINGLE_CYCLE ? module_sel : bus_wait_state;
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assign wbs_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
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assign wbs_dat_o = SINGLE_CYCLE ? rd_data_mux : rd_data_reg;
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assign wbs_dat_o = SINGLE_CYCLE ? rd_data_mux : rd_data_reg;
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assign wbs_err_o = !SINGLE_CYCLE && !module_sel && bus_wait_state;
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// generate acknowledge output signal, By using register all accesses takes two cycles.
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// generate acknowledge output signal, By using register all accesses takes two cycles.
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// Accesses in back to back clock cycles are not possable.
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// Accesses in back to back clock cycles are not possable.
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always @(posedge wbs_clk_i or negedge async_rst_b)
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always @(posedge wbs_clk_i or negedge async_rst_b)
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if (!async_rst_b)
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if (!async_rst_b)
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