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Line 38... |
////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module xgate_wbs_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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module xgate_wbs_bus #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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parameter DWIDTH = 16,
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parameter DWIDTH = 16,
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parameter WB_RD_DEFAULT = 0, // WISHBONE Read Bus default state
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parameter SINGLE_CYCLE = 1'b0)
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parameter SINGLE_CYCLE = 1'b0)
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(
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(
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// Wishbone Signals
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// Wishbone Signals
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output reg [DWIDTH-1:0] wbs_dat_o, // databus output - Pseudo Register
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output [DWIDTH-1:0] wbs_dat_o, // databus output - Pseudo Register
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output wbs_ack_o, // bus cycle acknowledge output
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output wbs_ack_o, // bus cycle acknowledge output
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output wbs_err_o, // bus error, lost module select durning wait state
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output wbs_err_o, // bus error, lost module select durning wait state
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input wbs_clk_i, // master clock input
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input wbs_clk_i, // master clock input
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input wbs_rst_i, // synchronous active high reset
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input wbs_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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input arst_i, // asynchronous reset
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input [ 5:1] wbs_adr_i, // lower address bits
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input [ 6:1] wbs_adr_i, // lower address bits
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input wbs_we_i, // write enable input
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input wbs_we_i, // write enable input
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input wbs_stb_i, // stobe/core select signal
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input wbs_stb_i, // stobe/core select signal
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input wbs_cyc_i, // valid bus cycle input
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input wbs_cyc_i, // valid bus cycle input
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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| Line 78... |
Line 79... |
output reg [1:0] write_xgr5, // Write Strobe for XGATE Data Register R5
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output reg [1:0] write_xgr5, // Write Strobe for XGATE Data Register R5
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output reg [1:0] write_xgr4, // Write Strobe for XGATE Data Register R4
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output reg [1:0] write_xgr4, // Write Strobe for XGATE Data Register R4
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output reg [1:0] write_xgr3, // Write Strobe for XGATE Data Register R3
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output reg [1:0] write_xgr3, // Write Strobe for XGATE Data Register R3
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output reg [1:0] write_xgr2, // Write Strobe for XGATE Data Register R2
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output reg [1:0] write_xgr2, // Write Strobe for XGATE Data Register R2
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output reg [1:0] write_xgr1, // Write Strobe for XGATE Data Register R1
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output reg [1:0] write_xgr1, // Write Strobe for XGATE Data Register R1
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output reg [1:0] write_irw_en_7, // Write Strobe for Interrupt Bypass Control Register 7
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output reg [1:0] write_irw_en_6, // Write Strobe for Interrupt Bypass Control Register 6
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output reg [1:0] write_irw_en_5, // Write Strobe for Interrupt Bypass Control Register 5
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output reg [1:0] write_irw_en_4, // Write Strobe for Interrupt Bypass Control Register 4
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output reg [1:0] write_irw_en_3, // Write Strobe for Interrupt Bypass Control Register 3
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output reg [1:0] write_irw_en_2, // Write Strobe for Interrupt Bypass Control Register 2
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output reg [1:0] write_irw_en_1, // Write Strobe for Interrupt Bypass Control Register 1
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output reg [1:0] write_irw_en_0, // Write Strobe for Interrupt Bypass Control Register 0
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output async_rst_b, //
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output async_rst_b, //
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output sync_reset, //
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output sync_reset, //
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input [415:0] read_regs // status register bits
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input [415:0] read_risc_regs, // status register bits for WISHBONE Read bus
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input [127:0] irq_bypass // IRQ status bits WISHBONE Read bus
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);
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);
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// registers
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// registers
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reg bus_wait_state; // Holdoff wbs_ack_o for one clock to add wait state
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reg bus_wait_state; // Holdoff wbs_ack_o for one clock to add wait state
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reg [4:0] addr_latch; // Capture WISHBONE Address
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reg [5:0] addr_latch; // Capture WISHBONE Address
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reg write_reserv1; // Dummy Reg decode for Reserved address
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reg write_reserv1; // Dummy Reg decode for Reserved address
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reg write_reserv2; // Dummy Reg decode for Reserved address
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reg write_reserv2; // Dummy Reg decode for Reserved address
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reg [DWIDTH-1:0] read_mux_irq; // Psudo register for WISHBONE IRQ read data bus mux
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// Wires
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// Wires
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wire module_sel; // This module is selected for bus transaction
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wire module_sel; // This module is selected for bus transaction
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wire wbs_wacc; // WISHBONE Write Strobe (Clock gating signal)
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wire wbs_wacc; // WISHBONE Write Strobe (Clock gating signal)
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wire wbs_racc; // WISHBONE Read Access (Clock gating signal)
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wire wbs_racc; // WISHBONE Read Access (Clock gating signal)
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wire [4:0] address; // Select either direct or latched address
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wire [5:0] address; // Select either direct or latched address
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reg [DWIDTH-1:0] read_mux_risc; // Pseudo regester for WISHBONE RISC read data bus mux
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//
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//
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// module body
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// module body
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//
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//
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Line 127... |
assign wbs_racc = module_sel && !wbs_we_i;
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assign wbs_racc = module_sel && !wbs_we_i;
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assign wbs_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
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assign wbs_ack_o = SINGLE_CYCLE ? module_sel : (bus_wait_state && module_sel);
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assign wbs_err_o = !SINGLE_CYCLE && !module_sel && bus_wait_state;
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assign wbs_err_o = !SINGLE_CYCLE && !module_sel && bus_wait_state;
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assign address = SINGLE_CYCLE ? wbs_adr_i : addr_latch;
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assign address = SINGLE_CYCLE ? wbs_adr_i : addr_latch;
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assign wbs_dat_o = read_mux_risc | read_mux_irq;
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// generate acknowledge output signal, By using register all accesses takes two cycles.
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// generate acknowledge output signal, By using register all accesses takes two cycles.
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// Accesses in back to back clock cycles are not possable.
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// Accesses in back to back clock cycles are not possible.
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always @(posedge wbs_clk_i or negedge async_rst_b)
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always @(posedge wbs_clk_i or negedge async_rst_b)
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if (!async_rst_b)
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if (!async_rst_b)
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bus_wait_state <= 1'b0;
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bus_wait_state <= 1'b0;
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else if (sync_reset)
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else if (sync_reset)
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bus_wait_state <= 1'b0;
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bus_wait_state <= 1'b0;
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Line 145... |
// Only used when Wait states are enabled
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// Only used when Wait states are enabled
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always @(posedge wbs_clk_i)
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always @(posedge wbs_clk_i)
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if ( module_sel ) // Clock gate for power saving
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if ( module_sel ) // Clock gate for power saving
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addr_latch <= wbs_adr_i;
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addr_latch <= wbs_adr_i;
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// WISHBONE Read Data Mux
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// WISHBONE Read Data Mux for RISC status and control registers
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always @*
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always @*
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case (address) // synopsys parallel_case
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case ({wbs_racc, address}) // synopsys parallel_case
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// 16 bit Bus, 16 bit Granularity
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// 16 bit Bus, 16 bit Granularity
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5'b0_0000: wbs_dat_o = read_regs[ 15: 0];
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7'b100_0000: read_mux_risc = read_risc_regs[ 15: 0];
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5'b0_0001: wbs_dat_o = read_regs[ 31: 16];
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7'b100_0001: read_mux_risc = read_risc_regs[ 31: 16];
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5'b0_0010: wbs_dat_o = read_regs[ 47: 32];
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7'b100_0010: read_mux_risc = read_risc_regs[ 47: 32];
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5'b0_0011: wbs_dat_o = read_regs[ 63: 48];
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7'b100_0011: read_mux_risc = read_risc_regs[ 63: 48];
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5'b0_0100: wbs_dat_o = read_regs[ 79: 64];
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7'b100_0100: read_mux_risc = read_risc_regs[ 79: 64];
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5'b0_0101: wbs_dat_o = read_regs[ 95: 80];
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7'b100_0101: read_mux_risc = read_risc_regs[ 95: 80];
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5'b0_0110: wbs_dat_o = read_regs[111: 96];
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7'b100_0110: read_mux_risc = read_risc_regs[111: 96];
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5'b0_0111: wbs_dat_o = read_regs[127:112];
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7'b100_0111: read_mux_risc = read_risc_regs[127:112];
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5'b0_1000: wbs_dat_o = read_regs[143:128];
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7'b100_1000: read_mux_risc = read_risc_regs[143:128];
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5'b0_1001: wbs_dat_o = read_regs[159:144];
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7'b100_1001: read_mux_risc = read_risc_regs[159:144];
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5'b0_1010: wbs_dat_o = read_regs[175:160];
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7'b100_1010: read_mux_risc = read_risc_regs[175:160];
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5'b0_1011: wbs_dat_o = read_regs[191:176];
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7'b100_1011: read_mux_risc = read_risc_regs[191:176];
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5'b0_1100: wbs_dat_o = read_regs[207:192];
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7'b100_1100: read_mux_risc = read_risc_regs[207:192];
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5'b0_1101: wbs_dat_o = read_regs[223:208];
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7'b100_1101: read_mux_risc = read_risc_regs[223:208];
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5'b0_1110: wbs_dat_o = read_regs[239:224];
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7'b100_1110: read_mux_risc = read_risc_regs[239:224];
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5'b0_1111: wbs_dat_o = read_regs[255:240];
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7'b100_1111: read_mux_risc = read_risc_regs[255:240];
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5'b1_0000: wbs_dat_o = read_regs[271:256];
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7'b101_0000: read_mux_risc = read_risc_regs[271:256];
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5'b1_0001: wbs_dat_o = read_regs[287:272];
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7'b101_0001: read_mux_risc = read_risc_regs[287:272];
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5'b1_0010: wbs_dat_o = read_regs[303:288];
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7'b101_0010: read_mux_risc = read_risc_regs[303:288];
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5'b1_0011: wbs_dat_o = read_regs[319:304];
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7'b101_0011: read_mux_risc = read_risc_regs[319:304];
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5'b1_0100: wbs_dat_o = read_regs[335:320];
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7'b101_0100: read_mux_risc = read_risc_regs[335:320];
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5'b1_0101: wbs_dat_o = read_regs[351:336];
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7'b101_0101: read_mux_risc = read_risc_regs[351:336];
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5'b1_0110: wbs_dat_o = read_regs[367:352];
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7'b101_0110: read_mux_risc = read_risc_regs[367:352];
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5'b1_0111: wbs_dat_o = read_regs[383:368];
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7'b101_0111: read_mux_risc = read_risc_regs[383:368];
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5'b1_1000: wbs_dat_o = read_regs[399:384];
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7'b101_1000: read_mux_risc = read_risc_regs[399:384];
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5'b1_1001: wbs_dat_o = read_regs[415:400];
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7'b101_1001: read_mux_risc = read_risc_regs[415:400];
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default: wbs_dat_o = 16'h0000;
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default: read_mux_risc = {DWIDTH{WB_RD_DEFAULT}};
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endcase
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endcase
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// generate wishbone write register strobes
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// generate wishbone write register strobes for Xgate RISC
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always @*
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always @*
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begin
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begin
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write_reserv1 = 1'b0;
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write_reserv1 = 1'b0;
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write_reserv2 = 1'b0;
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write_reserv2 = 1'b0;
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write_xgmctl = 1'b0;
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write_xgmctl = 1'b0;
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| Line 194... |
Line 210... |
write_xgr2 = 2'b00;
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write_xgr2 = 2'b00;
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write_xgr1 = 2'b00;
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write_xgr1 = 2'b00;
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if (wbs_wacc)
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if (wbs_wacc)
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case (address) // synopsys parallel_case
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case (address) // synopsys parallel_case
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// 16 bit Bus, 8 bit Granularity
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// 16 bit Bus, 8 bit Granularity
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5'b0_0000 : write_xgmctl = &wbs_sel_i;
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6'b00_0000 : write_xgmctl = &wbs_sel_i;
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5'b0_0001 : write_xgchid = wbs_sel_i[0];
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6'b00_0001 : write_xgchid = wbs_sel_i[0];
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5'b0_0010 : write_xgisp74 = 1'b1;
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6'b00_0010 : write_xgisp74 = 1'b1;
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5'b0_0011 : write_xgisp30 = 1'b1;
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6'b00_0011 : write_xgisp30 = 1'b1;
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5'b0_0100 : write_xgvbr = wbs_sel_i;
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6'b00_0100 : write_xgvbr = wbs_sel_i;
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5'b0_0101 : write_xgif_7 = wbs_sel_i;
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6'b00_0101 : write_xgif_7 = wbs_sel_i;
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5'b0_0110 : write_xgif_6 = wbs_sel_i;
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6'b00_0110 : write_xgif_6 = wbs_sel_i;
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5'b0_0111 : write_xgif_5 = wbs_sel_i;
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6'b00_0111 : write_xgif_5 = wbs_sel_i;
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5'b0_1000 : write_xgif_4 = wbs_sel_i;
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6'b00_1000 : write_xgif_4 = wbs_sel_i;
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5'b0_1001 : write_xgif_3 = wbs_sel_i;
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6'b00_1001 : write_xgif_3 = wbs_sel_i;
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5'b0_1010 : write_xgif_2 = wbs_sel_i;
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6'b00_1010 : write_xgif_2 = wbs_sel_i;
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5'b0_1011 : write_xgif_1 = wbs_sel_i;
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6'b00_1011 : write_xgif_1 = wbs_sel_i;
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5'b0_1100 : write_xgif_0 = wbs_sel_i;
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6'b00_1100 : write_xgif_0 = wbs_sel_i;
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5'b0_1101 : write_xgswt = &wbs_sel_i;
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6'b00_1101 : write_xgswt = &wbs_sel_i;
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5'b0_1110 : write_xgsem = &wbs_sel_i;
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6'b00_1110 : write_xgsem = &wbs_sel_i;
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5'b0_1111 : write_reserv1 = 1'b1;
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6'b00_1111 : write_reserv1 = 1'b1;
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5'b1_0000 : write_xgccr = wbs_sel_i[0];
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6'b01_0000 : write_xgccr = wbs_sel_i[0];
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5'b1_0001 : write_xgpc = wbs_sel_i;
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6'b01_0001 : write_xgpc = wbs_sel_i;
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5'b1_0010 : write_reserv2 = 1'b1;
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6'b01_0010 : write_reserv2 = 1'b1;
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5'b1_0011 : write_xgr1 = wbs_sel_i;
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6'b01_0011 : write_xgr1 = wbs_sel_i;
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5'b1_0100 : write_xgr2 = wbs_sel_i;
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6'b01_0100 : write_xgr2 = wbs_sel_i;
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5'b1_0101 : write_xgr3 = wbs_sel_i;
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6'b01_0101 : write_xgr3 = wbs_sel_i;
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5'b1_0110 : write_xgr4 = wbs_sel_i;
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6'b01_0110 : write_xgr4 = wbs_sel_i;
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5'b1_0111 : write_xgr5 = wbs_sel_i;
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6'b01_0111 : write_xgr5 = wbs_sel_i;
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5'b1_1000 : write_xgr6 = wbs_sel_i;
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6'b01_1000 : write_xgr6 = wbs_sel_i;
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5'b1_1001 : write_xgr7 = wbs_sel_i;
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6'b01_1001 : write_xgr7 = wbs_sel_i;
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default: ;
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endcase
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end
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// WISHBONE Read Data Mux for IRQ control registers
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always @*
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case ({wbs_racc, address}) // synopsys parallel_case
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// 16 bit Bus, 16 bit Granularity
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7'b110_0000: read_mux_irq = irq_bypass[ 15: 0];
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7'b110_0001: read_mux_irq = irq_bypass[ 31: 16];
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7'b110_0010: read_mux_irq = irq_bypass[ 47: 32];
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7'b110_0011: read_mux_irq = irq_bypass[ 63: 48];
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7'b110_0100: read_mux_irq = irq_bypass[ 79: 64];
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7'b110_0101: read_mux_irq = irq_bypass[ 95: 80];
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7'b110_0110: read_mux_irq = irq_bypass[111: 96];
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7'b110_0111: read_mux_irq = irq_bypass[127:112];
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default: read_mux_irq = {DWIDTH{WB_RD_DEFAULT}};
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endcase
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// generate wishbone write register strobes for interrupt control
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always @*
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begin
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write_irw_en_7 = 2'b00;
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write_irw_en_6 = 2'b00;
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write_irw_en_5 = 2'b00;
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write_irw_en_4 = 2'b00;
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write_irw_en_3 = 2'b00;
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write_irw_en_2 = 2'b00;
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write_irw_en_1 = 2'b00;
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write_irw_en_0 = 2'b00;
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if (wbs_wacc)
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case (address) // synopsys parallel_case
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// 16 bit Bus, 8 bit Granularity
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6'b10_0000 : write_irw_en_0 = wbs_sel_i;
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6'b10_0001 : write_irw_en_1 = wbs_sel_i;
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6'b10_0010 : write_irw_en_2 = wbs_sel_i;
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6'b10_0011 : write_irw_en_3 = wbs_sel_i;
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6'b10_0100 : write_irw_en_4 = wbs_sel_i;
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6'b10_0101 : write_irw_en_5 = wbs_sel_i;
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6'b10_0110 : write_irw_en_6 = wbs_sel_i;
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6'b10_0111 : write_irw_en_7 = wbs_sel_i;
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default: ;
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default: ;
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endcase
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endcase
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end
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end
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endmodule // xgate_wbs_bus
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endmodule // xgate_wbs_bus
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