| Line 90... |
Line 90... |
output reg [1:0] write_irw_en_1, // Write Strobe for Interrupt Bypass Control Register 1
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output reg [1:0] write_irw_en_1, // Write Strobe for Interrupt Bypass Control Register 1
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output reg [1:0] write_irw_en_0, // Write Strobe for Interrupt Bypass Control Register 0
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output reg [1:0] write_irw_en_0, // Write Strobe for Interrupt Bypass Control Register 0
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output async_rst_b, //
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output async_rst_b, //
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output sync_reset, //
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output sync_reset, //
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input [415:0] read_risc_regs, // status register bits for WISHBONE Read bus
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input [415:0] read_risc_regs, // status register bits for WISHBONE Read bus
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input [127:0] irq_bypass // IRQ status bits WISHBONE Read bus
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input [127:1] irq_bypass // IRQ status bits WISHBONE Read bus
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);
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);
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// registers
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// registers
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reg bus_wait_state; // Holdoff wbs_ack_o for one clock to add wait state
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reg bus_wait_state; // Holdoff wbs_ack_o for one clock to add wait state
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| Line 244... |
Line 244... |
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// WISHBONE Read Data Mux for IRQ control registers
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// WISHBONE Read Data Mux for IRQ control registers
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always @*
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always @*
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case ({wbs_racc, address}) // synopsys parallel_case
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case ({wbs_racc, address}) // synopsys parallel_case
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// 16 bit Bus, 16 bit Granularity
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// 16 bit Bus, 16 bit Granularity
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7'b110_0000: read_mux_irq = irq_bypass[ 15: 0];
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7'b110_0000: read_mux_irq = {irq_bypass[ 15: 1], 1'b0};
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7'b110_0001: read_mux_irq = irq_bypass[ 31: 16];
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7'b110_0001: read_mux_irq = irq_bypass[ 31: 16];
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7'b110_0010: read_mux_irq = irq_bypass[ 47: 32];
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7'b110_0010: read_mux_irq = irq_bypass[ 47: 32];
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7'b110_0011: read_mux_irq = irq_bypass[ 63: 48];
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7'b110_0011: read_mux_irq = irq_bypass[ 63: 48];
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7'b110_0100: read_mux_irq = irq_bypass[ 79: 64];
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7'b110_0100: read_mux_irq = irq_bypass[ 79: 64];
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7'b110_0101: read_mux_irq = irq_bypass[ 95: 80];
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7'b110_0101: read_mux_irq = irq_bypass[ 95: 80];
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