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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_wbs_bus.v] - Diff between revs 89 and 96
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| Rev 89 |
Rev 96 |
| Line 49... |
Line 49... |
output wbs_err_o, // bus error, lost module select durning wait state
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output wbs_err_o, // bus error, lost module select durning wait state
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input wbs_clk_i, // master clock input
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input wbs_clk_i, // master clock input
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input wbs_rst_i, // synchronous active high reset
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input wbs_rst_i, // synchronous active high reset
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input arst_i, // asynchronous reset
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input arst_i, // asynchronous reset
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input [ 6:1] wbs_adr_i, // lower address bits
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input [ 6:1] wbs_adr_i, // lower address bits
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input [DWIDTH-1:0] wbs_dat_i, // databus input
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input wbs_we_i, // write enable input
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input wbs_we_i, // write enable input
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input wbs_stb_i, // stobe/core select signal
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input wbs_stb_i, // stobe/core select signal
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input wbs_cyc_i, // valid bus cycle input
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input wbs_cyc_i, // valid bus cycle input
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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input [1:0] wbs_sel_i, // Select byte in word bus transaction
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// XGATE Control Signals
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// XGATE Control Signals
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