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[/] [xgate/] [trunk/] [sim/] [verilog/] [run/] [run_iverilog] - Diff between revs 5 and 32
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| Rev 5 |
Rev 32 |
| Line 18... |
Line 18... |
$xgate/rtl/verilog/xgate_regs.v \
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$xgate/rtl/verilog/xgate_regs.v \
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$xgate/rtl/verilog/xgate_risc.v \
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$xgate/rtl/verilog/xgate_risc.v \
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$xgate/rtl/verilog/xgate_irq_encode.v \
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$xgate/rtl/verilog/xgate_irq_encode.v \
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\
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\
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$bench/verilog/wb_master_model.v \
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$bench/verilog/wb_master_model.v \
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$bench/verilog/ram.v \
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$bench/verilog/tst_bench_top.v
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$bench/verilog/tst_bench_top.v
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@ good_compile = $status
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@ good_compile = $status
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if ($good_compile == 0) then
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if ($good_compile == 0) then
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