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https://opencores.org/ocsvn/xgate/xgate/trunk
[/] [xgate/] [trunk/] [sim/] [verilog/] [run/] [run_iverilog] - Diff between revs 32 and 89
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| Rev 32 |
Rev 89 |
| Line 16... |
Line 16... |
$xgate/rtl/verilog/xgate_wbs_bus.v \
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$xgate/rtl/verilog/xgate_wbs_bus.v \
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$xgate/rtl/verilog/xgate_wbm_bus.v \
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$xgate/rtl/verilog/xgate_wbm_bus.v \
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$xgate/rtl/verilog/xgate_regs.v \
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$xgate/rtl/verilog/xgate_regs.v \
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$xgate/rtl/verilog/xgate_risc.v \
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$xgate/rtl/verilog/xgate_risc.v \
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$xgate/rtl/verilog/xgate_irq_encode.v \
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$xgate/rtl/verilog/xgate_irq_encode.v \
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$xgate/rtl/verilog/xgate_jtag.v \
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\
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$bench/verilog/wb_master_model.v \
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$bench/verilog/wb_master_model.v \
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$bench/verilog/ram.v \
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$bench/verilog/ram.v \
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$bench/verilog/tst_bench_top.v
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$bench/verilog/tst_bench_top.v
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