URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [sw/] [xgate_test_code/] [debug_test/] [debug_test.s] - Diff between revs 16 and 52

Rev 16	Rev 52
Line 80...	Line 80...


`; Test`	`; Test`
`LDL R4,#$c3 ;`	`LDL R4,#$c3 ;`
`STW R4,(R0,#$08) ;`	`STW R4,(R0,#$08) ;`
`LDL R3,#$01 ; R3 = $01`	`LDL R7,#$01 ; R3 = $01; R7 = $01`

`BRK ; Enter Debug mode and start doing Single Step Commands`	`BRK ; Enter Debug mode and start doing Single Step Commands`
`; from the testbench. Verify PC and R3 values.`	`; from the testbench. Verify PC and R3 values.`

`ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $02)`	`ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $02)`
Line 146...	Line 146...
`LDL R4,#$01 ; R4 = $01`	`LDL R4,#$01 ; R4 = $01`
`LDL R7,#$03 ; R7 = $03`	`LDL R7,#$03 ; R7 = $03`

`_T2_LOOP`	`_T2_LOOP`
`ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $02)`	`ADDL R3,#$01 ; R3 + $01 => R3 (R3 = $02)`
`NOP`	`COM R6 ; Toggle R6`
`BRA _T2_LOOP ; Create an infinate loop. The testbench will`	`BRA _T2_LOOP ; Create an infinate loop. The testbench will`
`; take control using the Debug bit and change`	`; take control using the Debug bit and change`
`; the PC to exit the loop.`	`; the PC to exit the loop.`

`NOP`	`NOP`