| Line 160... |
Line 160... |
DC.W _ERROR ; point to start address
|
DC.W _ERROR ; point to start address
|
DC.W V_PTR ; point to initial variables
|
DC.W V_PTR ; point to initial variables
|
|
|
ORG $2000 ; with comment
|
ORG $2000 ; with comment
|
|
|
V_PTR EQU 123
|
V_PTR EQU 123
|
|
|
DC.W BACK_
|
DC.W BACK_
|
DS.W 8
|
DS.W 8
|
DC.B $56
|
DC.B $56
|
DS.B 11
|
DS.B 11
|
| Line 210... |
Line 210... |
BCS _FAIL ; Carry should be clear
|
BCS _FAIL ; Carry should be clear
|
BVS _FAIL ; Overflow Flag should be clear
|
BVS _FAIL ; Overflow Flag should be clear
|
SUB R0,R0,R4 ; R4 Should be zero
|
SUB R0,R0,R4 ; R4 Should be zero
|
BNE _FAIL
|
BNE _FAIL
|
|
|
; Test ASR instruction
|
; Test ASR instruction **************************************************
|
LDL R5,#$04 ; R5=$0008
|
LDL R5,#$04 ; R5=$0008
|
LDH R5,#$81 ; R5=$8108
|
LDH R5,#$81 ; R5=$8108
|
LDL R3,#$03
|
LDL R3,#$03
|
ASR R5,R3 ; R5=$f000, Carry flag set
|
ASR R5,R3 ; R5=$f000, Carry flag set
|
BCC _FAIL
|
BCC _FAIL
|
| Line 222... |
Line 222... |
LDL R4,#$20 ; R4=$0020
|
LDL R4,#$20 ; R4=$0020
|
LDH R4,#$f0 ; R4=$f020
|
LDH R4,#$f0 ; R4=$f020
|
SUB R0,R5,R4 ; Compare R5 to R4
|
SUB R0,R5,R4 ; Compare R5 to R4
|
BNE _FAIL
|
BNE _FAIL
|
|
|
; Test CSL insrtruction
|
; Test CSL instruction **************************************************
|
LDL R5,#$10 ; R5=$0010
|
LDL R5,#$10 ; R5=$0010
|
LDH R5,#$88 ; R5=$8810
|
LDH R5,#$88 ; R5=$8810
|
LDL R3,#$05
|
LDL R3,#$05
|
CSL R5,R3 ; R5=$081f, Carry flag set
|
CSL R5,R3 ; R5=$081f, Carry flag set
|
BCC _FAIL
|
BCC _FAIL
|
LDL R4,#$00 ; R4=$0000
|
LDL R4,#$00 ; R4=$0000
|
LDH R4,#$02 ; R4=$0200
|
LDH R4,#$02 ; R4=$0200
|
SUB R0,R5,R4 ; Compare R5 to R4
|
SUB R0,R5,R4 ; Compare R5 to R4
|
BNE _FAIL
|
BNE _FAIL
|
|
|
;Test CSR instruction
|
;Test CSR instruction ***************************************************
|
LDL R5,#$88 ; R5=$0088
|
LDL R5,#$88 ; R5=$0088
|
LDH R5,#$10 ; R5=$1088
|
LDH R5,#$10 ; R5=$1088
|
LDL R3,#$04
|
LDL R3,#$04
|
CSR R5,R3 ; R5=$0108, Carry flag set
|
CSR R5,R3 ; R5=$0108, Carry flag set
|
BCC _FAIL
|
BCC _FAIL
|
LDL R4,#$08 ; R4=$0008
|
LDL R4,#$08 ; R4=$0008
|
LDH R4,#$01 ; R4=$0108
|
LDH R4,#$01 ; R4=$0108
|
SUB R0,R5,R4 ; Compare R5 to R4
|
SUB R0,R5,R4 ; Compare R5 to R4
|
BNE _FAIL
|
BNE _FAIL
|
|
|
;Test LSL instruction
|
;Test LSL instruction ***************************************************
|
LDL R2,#$ff ; R2=$00ff
|
LDL R2,#$ff ; R2=$00ff
|
LDH R2,#$07 ; R2=$07ff
|
LDH R2,#$07 ; R2=$07ff
|
LDL R1,#$06
|
LDL R1,#$06
|
LSL R2,R1 ; R2=$ffc0, Carry flag set
|
LSL R2,R1 ; R2=$ffc0, Carry flag set
|
BCC _FAIL
|
BCC _FAIL
|
LDL R4,#$c0 ; R4=$0008
|
LDL R4,#$c0 ; R4=$0008
|
LDH R4,#$ff ; R4=$0108
|
LDH R4,#$ff ; R4=$0108
|
SUB R0,R2,R4 ; Compare R2 to R4
|
SUB R0,R2,R4 ; Compare R2 to R4
|
BNE _FAIL
|
BNE _FAIL
|
|
|
;Test LSR instruction
|
;Test LSR instruction ***************************************************
|
LDL R7,#$02 ; R7=$0002
|
LDL R7,#$02 ; R7=$0002
|
LDH R7,#$c3 ; R7=$c302
|
LDH R7,#$c3 ; R7=$c302
|
LDL R6,#$02
|
LDL R6,#$02
|
LSR R7,R6 ; R7=$30c0, Carry flag set
|
LSR R7,R6 ; R7=$30c0, Carry flag set
|
BCC _FAIL
|
BCC _FAIL
|
LDL R4,#$c0 ; R4=$00c0
|
LDL R4,#$c0 ; R4=$00c0
|
LDH R4,#$30 ; R4=$30c0
|
LDH R4,#$30 ; R4=$30c0
|
SUB R0,R7,R4 ; Compare R7 to R4
|
SUB R0,R7,R4 ; Compare R7 to R4
|
BNE _FAIL
|
BNE _FAIL
|
|
|
;Test ROL instruction
|
;Test ROL instruction ***************************************************
|
LDL R7,#$62 ; R7=$0062
|
LDL R7,#$62 ; R7=$0062
|
LDH R7,#$c3 ; R7=$c362
|
LDH R7,#$c3 ; R7=$c362
|
LDL R6,#$04
|
LDL R6,#$04
|
ROL R7,R6 ; R7=$362c
|
ROL R7,R6 ; R7=$362c
|
BVS _FAIL ; Overflow Flag should be clear
|
BVS _FAIL ; Overflow Flag should be clear
|
LDL R4,#$2c ; R4=$002c
|
LDL R4,#$2c ; R4=$002c
|
LDH R4,#$36 ; R4=$362c
|
LDH R4,#$36 ; R4=$362c
|
SUB R0,R7,R4 ; Compare R7 to R4
|
SUB R0,R7,R4 ; Compare R7 to R4
|
BNE _FAIL
|
BNE _FAIL
|
|
|
;Test ROR instruction
|
;Test ROR instruction ***************************************************
|
LDL R7,#$62 ; R7=$0062
|
LDL R7,#$62 ; R7=$0062
|
LDH R7,#$c3 ; R7=$c362
|
LDH R7,#$c3 ; R7=$c362
|
LDL R6,#$08
|
LDL R6,#$08
|
ROL R7,R6 ; R7=$62c3
|
ROR R7,R6 ; R7=$62c3
|
BVS _FAIL ; Overflow Flag should be clear
|
BVS _FAIL ; Overflow Flag should be clear
|
LDL R4,#$c3 ; R4=$00c3
|
LDL R4,#$c3 ; R4=$00c3
|
LDH R4,#$62 ; R4=$62c3
|
LDH R4,#$62 ; R4=$62c3
|
SUB R0,R7,R4 ; Compare R7 to R4
|
SUB R0,R7,R4 ; Compare R7 to R4
|
BNE _FAIL
|
BNE _FAIL
|
|
|
; Test ASR instruction
|
; Test ASR instruction **************************************************
|
LDL R5,#$00 ; R5=$0000
|
LDL R5,#$00 ; R5=$0000
|
LDH R5,#$80 ; R5=$8000
|
LDH R5,#$80 ; R5=$8000
|
ASR R5,#0 ; R5=$ffff, Carry flag set
|
ASR R5,#0 ; R5=$ffff, Carry flag set
|
BCC _FAIL
|
BCC _FAIL
|
BVS _FAIL ; Overflow Flag should be clear
|
BVS _FAIL ; Overflow Flag should be clear
|
| Line 309... |
Line 309... |
LDL R4,#$00 ; R4=$0000
|
LDL R4,#$00 ; R4=$0000
|
LDH R4,#$00 ; R4=$0000
|
LDH R4,#$00 ; R4=$0000
|
SUB R0,R5,R4 ; Compare R5 to R4
|
SUB R0,R5,R4 ; Compare R5 to R4
|
BNE _FAIL
|
BNE _FAIL
|
|
|
;Test CSR instruction
|
;Test CSR instruction ***************************************************
|
LDL R5,#$ff ; R5=$00ff
|
LDL R5,#$ff ; R5=$00ff
|
LDH R5,#$80 ; R5=$80ff
|
LDH R5,#$80 ; R5=$80ff
|
CSR R5,#15 ; R5=$0001, Carry flag clear
|
CSR R5,#15 ; R5=$0001, Carry flag clear
|
BCS _FAIL
|
BCS _FAIL
|
LDL R4,#$01 ; R4=$0001
|
LDL R4,#$01 ; R4=$0001
|
LDH R4,#$00 ; R4=$0001
|
LDH R4,#$00 ; R4=$0001
|
SUB R0,R5,R4 ; Compare R5 to R4
|
SUB R0,R5,R4 ; Compare R5 to R4
|
BNE _FAIL
|
BNE _FAIL
|
|
|
;Test LSL instruction
|
;Test LSL instruction ***************************************************
|
LDL R2,#$1a ; R2=$001a
|
LDL R2,#$1a ; R2=$001a
|
LDH R2,#$ff ; R2=$ff1a
|
LDH R2,#$ff ; R2=$ff1a
|
LSL R2,#12 ; R2=$a000, Carry flag set
|
LSL R2,#12 ; R2=$a000, Carry flag set
|
BCC _FAIL
|
BCC _FAIL
|
LDL R4,#$00 ; R4=$0000
|
LDL R4,#$00 ; R4=$0000
|
LDH R4,#$a0 ; R4=$a000
|
LDH R4,#$a0 ; R4=$a000
|
SUB R0,R2,R4 ; Compare R2 to R4
|
SUB R0,R2,R4 ; Compare R2 to R4
|
BNE _FAIL
|
BNE _FAIL
|
|
|
;Test LSR instruction
|
;Test LSR instruction ***************************************************
|
LDL R7,#$8f ; R7=$008f
|
LDL R7,#$8f ; R7=$008f
|
LDH R7,#$b2 ; R7=$b18f
|
LDH R7,#$b2 ; R7=$b18f
|
LSR R7,#8 ; R7=$00b0, Carry flag set
|
LSR R7,#8 ; R7=$00b0, Carry flag set
|
BCC _FAIL
|
BCC _FAIL
|
LDL R4,#$b2 ; R4=$00b0
|
LDL R4,#$b2 ; R4=$00b0
|
LDH R4,#$00 ; R4=$00b0
|
LDH R4,#$00 ; R4=$00b0
|
SUB R0,R7,R4 ; Compare R7 to R4
|
SUB R0,R7,R4 ; Compare R7 to R4
|
BNE _FAIL
|
BNE _FAIL
|
|
|
;Test ROL instruction
|
;Test ROL instruction ***************************************************
|
LDL R7,#$62 ; R7=$0062
|
LDL R7,#$62 ; R7=$0062
|
LDH R7,#$c3 ; R7=$c362
|
LDH R7,#$c3 ; R7=$c362
|
ROL R7,#8 ; R7=$62c3
|
ROL R7,#8 ; R7=$62c3
|
BVS _FAIL ; Overflow Flag should be clear
|
BVS _FAIL ; Overflow Flag should be clear
|
LDL R4,#$c3 ; R4=$00c3
|
LDL R4,#$c3 ; R4=$00c3
|
LDH R4,#$62 ; R4=$62c3
|
LDH R4,#$62 ; R4=$62c3
|
SUB R0,R7,R4 ; Compare R7 to R4
|
SUB R0,R7,R4 ; Compare R7 to R4
|
BNE _FAIL
|
BNE _FAIL
|
|
|
;Test ROR instruction
|
;Test ROR instruction ***************************************************
|
LDL R7,#$62 ; R7=$0062
|
LDL R7,#$62 ; R7=$0062
|
LDH R7,#$c3 ; R7=$c362
|
LDH R7,#$c3 ; R7=$c362
|
ROL R7,#12 ; R7=$2c36
|
ROR R7,#12 ; R7=$362c
|
BVS _FAIL ; Overflow Flag should be clear
|
BVS _FAIL ; Overflow Flag should be clear
|
LDL R4,#$36 ; R4=$0036
|
LDL R4,#$2c ; R4=$002c
|
LDH R4,#$2c ; R4=$2c36
|
LDH R4,#$36 ; R4=$362c
|
SUB R0,R7,R4 ; Compare R7 to R4
|
SUB R0,R7,R4 ; Compare R7 to R4
|
BNE _FAIL
|
BNE _FAIL
|
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
LDH R2,#$80
|
LDH R2,#$80
|
| Line 389... |
Line 389... |
LDL R3,#$03 ; Checkpoint Value
|
LDL R3,#$03 ; Checkpoint Value
|
STB R3,(R2,#0)
|
STB R3,(R2,#0)
|
LDL R3,#$02 ; Thread Value
|
LDL R3,#$02 ; Thread Value
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
|
|
;Test ANDL instruction
|
;Test ANDL instruction **************************************************
|
LDL R7,#$55 ; R7=$0055
|
LDL R7,#$55 ; R7=$0055
|
LDH R7,#$a5 ; R7=$a555
|
LDH R7,#$a5 ; R7=$a555
|
ANDL R7,#$00 ; R7=&a500
|
ANDL R7,#$00 ; R7=&a500
|
BNE _FAIL2 ; Zero Flag should be set
|
BNE _FAIL2 ; Zero Flag should be set
|
BVS _FAIL2 ; Overflow Flag should be clear
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| Line 411... |
Line 411... |
LDL R3,#$80 ; R3=$0080
|
LDL R3,#$80 ; R3=$0080
|
LDH R3,#$a5 ; R3=$a580
|
LDH R3,#$a5 ; R3=$a580
|
SUB R0,R7,R3 ; Compare R7 to R3
|
SUB R0,R7,R3 ; Compare R7 to R3
|
BNE _FAIL2
|
BNE _FAIL2
|
|
|
;Test ANDH instruction
|
;Test ANDH instruction **************************************************
|
LDL R7,#$55 ; R7=$0055
|
LDL R7,#$55 ; R7=$0055
|
LDH R7,#$a5 ; R7=$a555
|
LDH R7,#$a5 ; R7=$a555
|
ANDH R7,#$00 ; R7=&0055
|
ANDH R7,#$00 ; R7=&0055
|
BNE _FAIL2 ; Zero Flag should be set
|
BNE _FAIL2 ; Zero Flag should be set
|
BVS _FAIL2 ; Overflow Flag should be clear
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| Line 433... |
Line 433... |
LDL R3,#$c5 ; R3=$00c5
|
LDL R3,#$c5 ; R3=$00c5
|
LDH R3,#$80 ; R3=$80c5
|
LDH R3,#$80 ; R3=$80c5
|
SUB R0,R7,R3 ; Compare R7 to R3
|
SUB R0,R7,R3 ; Compare R7 to R3
|
BNE _FAIL2
|
BNE _FAIL2
|
|
|
;Test BITL instruction
|
;Test BITL instruction **************************************************
|
LDL R7,#$55 ; R7=$0055
|
LDL R7,#$55 ; R7=$0055
|
LDH R7,#$a5 ; R7=$a555
|
LDH R7,#$a5 ; R7=$a555
|
BITL R7,#$00 ; R7=&a500
|
BITL R7,#$00 ; R7=&a500
|
BNE _FAIL2 ; Zero Flag should be set
|
BNE _FAIL2 ; Zero Flag should be set
|
BVS _FAIL2 ; Overflow Flag should be clear
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| Line 447... |
Line 447... |
BITL R7,#$80 ; R7=$a580
|
BITL R7,#$80 ; R7=$a580
|
BPL _FAIL2 ; Negative Flag should be set
|
BPL _FAIL2 ; Negative Flag should be set
|
BEQ _FAIL2 ; Zero Flag should be clear
|
BEQ _FAIL2 ; Zero Flag should be clear
|
BVS _FAIL2 ; Overflow Flag should be clear
|
BVS _FAIL2 ; Overflow Flag should be clear
|
|
|
;Test BITH instruction
|
;Test BITH instruction **************************************************
|
LDL R7,#$55 ; R7=$0055
|
LDL R7,#$55 ; R7=$0055
|
LDH R7,#$a5 ; R7=$a555
|
LDH R7,#$a5 ; R7=$a555
|
BITH R7,#$00 ; R7=&0055
|
BITH R7,#$00 ; R7=&0055
|
BNE _FAIL2 ; Zero Flag should be set
|
BNE _FAIL2 ; Zero Flag should be set
|
BVS _FAIL2 ; Overflow Flag should be clear
|
BVS _FAIL2 ; Overflow Flag should be clear
|
| Line 461... |
Line 461... |
BITH R7,#$80 ; R7=$80c5
|
BITH R7,#$80 ; R7=$80c5
|
BPL _FAIL2 ; Negative Flag should be set
|
BPL _FAIL2 ; Negative Flag should be set
|
BEQ _FAIL2 ; Zero Flag should be clear
|
BEQ _FAIL2 ; Zero Flag should be clear
|
BVS _FAIL2 ; Overflow Flag should be clear
|
BVS _FAIL2 ; Overflow Flag should be clear
|
|
|
;Test ORL instruction
|
;Test ORL instruction ***************************************************
|
LDL R2,#$0b
|
LDL R2,#$0b
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
LDL R7,#$00 ; R7=$0000
|
LDL R7,#$00 ; R7=$0000
|
LDH R7,#$a5 ; R7=$a500
|
LDH R7,#$a5 ; R7=$a500
|
ORL R7,#$00 ; R7=&a500
|
ORL R7,#$00 ; R7=&a500
|
| Line 489... |
Line 489... |
LDL R3,#$ff ; R3=$00ff
|
LDL R3,#$ff ; R3=$00ff
|
LDH R3,#$a5 ; R3=$a5ff
|
LDH R3,#$a5 ; R3=$a5ff
|
SUB R0,R7,R3 ; Compare R7 to R3
|
SUB R0,R7,R3 ; Compare R7 to R3
|
BNE _FAIL2
|
BNE _FAIL2
|
|
|
;Test ORH instruction
|
;Test ORH instruction ***************************************************
|
LDL R2,#$0b
|
LDL R2,#$0b
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
LDL R7,#$88 ; R7=$0088
|
LDL R7,#$88 ; R7=$0088
|
LDH R7,#$00 ; R7=$0088
|
LDH R7,#$00 ; R7=$0088
|
ORH R7,#$00 ; R7=&0088
|
ORH R7,#$00 ; R7=&0088
|
| Line 517... |
Line 517... |
LDL R3,#$36 ; R3=$0036
|
LDL R3,#$36 ; R3=$0036
|
LDH R3,#$f1 ; R3=$f136
|
LDH R3,#$f1 ; R3=$f136
|
SUB R0,R7,R3 ; Compare R7 to R3
|
SUB R0,R7,R3 ; Compare R7 to R3
|
BNE _FAIL2
|
BNE _FAIL2
|
|
|
;Test XNORL instruction
|
;Test XNORL instruction *************************************************
|
LDL R2,#$0b
|
LDL R2,#$0b
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
LDL R7,#$c3 ; R7=$00c3
|
LDL R7,#$c3 ; R7=$00c3
|
LDH R7,#$96 ; R7=$96c3
|
LDH R7,#$96 ; R7=$96c3
|
XNORL R7,#$3c ; R7=$9600
|
XNORL R7,#$3c ; R7=$9600
|
| Line 545... |
Line 545... |
LDL R3,#$8c ; R3=$008c
|
LDL R3,#$8c ; R3=$008c
|
LDH R3,#$a5 ; R3=$a58c
|
LDH R3,#$a5 ; R3=$a58c
|
SUB R0,R6,R3 ; Compare R6 to R3
|
SUB R0,R6,R3 ; Compare R6 to R3
|
BNE _FAIL2
|
BNE _FAIL2
|
|
|
;Test XNORH instruction
|
;Test XNORH instruction *************************************************
|
LDL R2,#$0b
|
LDL R2,#$0b
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
LDL R7,#$c3 ; R7=$00c3
|
LDL R7,#$c3 ; R7=$00c3
|
LDH R7,#$96 ; R7=$96c3
|
LDH R7,#$96 ; R7=$96c3
|
XNORH R7,#$69 ; R7=$00c3
|
XNORH R7,#$69 ; R7=$00c3
|
| Line 602... |
Line 602... |
LDL R3,#$05 ; Checkpoint Value
|
LDL R3,#$05 ; Checkpoint Value
|
STB R3,(R2,#0)
|
STB R3,(R2,#0)
|
LDL R3,#$03 ; Thread Value
|
LDL R3,#$03 ; Thread Value
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
|
|
;Test SEX instruction
|
;Test SEX instruction ***************************************************
|
LDL R2,#$0b
|
LDL R2,#$0b
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
LDL R3,#$00 ; R3=$0000
|
LDL R3,#$00 ; R3=$0000
|
LDH R3,#$ff ; R3=$ff00
|
LDH R3,#$ff ; R3=$ff00
|
SEX R3 ; R3=$0000
|
SEX R3 ; R3=$0000
|
| Line 630... |
Line 630... |
LDL R3,#$83 ; R3=$0083
|
LDL R3,#$83 ; R3=$0083
|
LDH R3,#$ff ; R3=$ff83
|
LDH R3,#$ff ; R3=$ff83
|
SUB R0,R6,R3 ; Compare R6 to R3
|
SUB R0,R6,R3 ; Compare R6 to R3
|
BNE _FAIL3
|
BNE _FAIL3
|
|
|
;Test PAR instruction
|
;Test PAR instruction ***************************************************
|
LDL R2,#$0a
|
LDL R2,#$0a
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
LDL R4,#$00 ; R4=$0000
|
LDL R4,#$00 ; R4=$0000
|
LDH R4,#$00 ; R4=$0000
|
LDH R4,#$00 ; R4=$0000
|
PAR R4 ; R4=$0000
|
PAR R4 ; R4=$0000
|
| Line 658... |
Line 658... |
LDL R3,#$01 ; R3=$0001
|
LDL R3,#$01 ; R3=$0001
|
LDH R3,#$03 ; R3=$0301
|
LDH R3,#$03 ; R3=$0301
|
SUB R0,R6,R3 ; Compare R6 to R3
|
SUB R0,R6,R3 ; Compare R6 to R3
|
BNE _FAIL3
|
BNE _FAIL3
|
|
|
;Test AND instruction
|
;Test AND instruction ***************************************************
|
LDL R2,#$0a
|
LDL R2,#$0a
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
LDL R6,#$55 ; R6=$0055
|
LDL R6,#$55 ; R6=$0055
|
LDH R6,#$aa ; R6=$aa55
|
LDH R6,#$aa ; R6=$aa55
|
LDL R5,#$aa ; R5=$00aa
|
LDL R5,#$aa ; R5=$00aa
|
| Line 684... |
Line 684... |
BVS _FAIL3 ; Overflow Flag should be clear
|
BVS _FAIL3 ; Overflow Flag should be clear
|
BCC _FAIL3 ; Carry Flag should be set
|
BCC _FAIL3 ; Carry Flag should be set
|
SUB R0,R4,R7 ; Compare R4 to R7
|
SUB R0,R4,R7 ; Compare R4 to R7
|
BNE _FAIL2
|
BNE _FAIL2
|
|
|
;Test OR instruction
|
;Test OR instruction ****************************************************
|
LDL R2,#$0a
|
LDL R2,#$0a
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
LDL R6,#$00 ; R6=$0000
|
LDL R6,#$00 ; R6=$0000
|
LDL R5,#$00 ; R5=$0000
|
LDL R5,#$00 ; R5=$0000
|
OR R3,R5,R6 ; R3=$0000
|
OR R3,R5,R6 ; R3=$0000
|
| Line 712... |
Line 712... |
LDL R3,#$df ; R3=$00df
|
LDL R3,#$df ; R3=$00df
|
LDH R3,#$ba ; R3=$badf
|
LDH R3,#$ba ; R3=$badf
|
SUB R0,R4,R3 ; Compare R6 to R3
|
SUB R0,R4,R3 ; Compare R6 to R3
|
BNE _FAIL3
|
BNE _FAIL3
|
|
|
;Test XNOR instruction
|
;Test XNOR instruction **************************************************
|
LDL R2,#$0a
|
LDL R2,#$0a
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
LDL R1,#$55 ; R1=$0055
|
LDL R1,#$55 ; R1=$0055
|
LDH R1,#$aa ; R1=$aa55
|
LDH R1,#$aa ; R1=$aa55
|
LDL R5,#$aa ; R5=$00aa
|
LDL R5,#$aa ; R5=$00aa
|
| Line 742... |
Line 742... |
LDH R3,#$8c ; R3=$8c32
|
LDH R3,#$8c ; R3=$8c32
|
SUB R0,R4,R3 ; Compare R4 to R3
|
SUB R0,R4,R3 ; Compare R4 to R3
|
BNE _FAIL3
|
BNE _FAIL3
|
|
|
|
|
|
;Test TFR instruction ***************************************************
|
|
MOV R1,R0
|
|
COM R1
|
|
TFR CCR,R1 ; Negative=1, Zero=1, Overflow=1, Carry=1
|
|
TFR R5,CCR ; R5=$000f
|
|
LDL R6,#$0f ; R6=$xx0f
|
|
LDH R6,#$00 ; R5=$000f
|
|
CMP R5,R6
|
|
BNE _FAIL3
|
|
|
|
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
LDH R2,#$80
|
LDH R2,#$80
|
LDL R3,#$06
|
LDL R3,#$06
|
STB R3,(R2,#0)
|
STB R3,(R2,#0)
|
|
|
| Line 772... |
Line 783... |
LDL R3,#$07 ; Checkpoint Value
|
LDL R3,#$07 ; Checkpoint Value
|
STB R3,(R2,#0)
|
STB R3,(R2,#0)
|
LDL R3,#$04 ; Thread Value
|
LDL R3,#$04 ; Thread Value
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
|
|
;Test BFEXT instruction
|
;Test BFEXT instruction *************************************************
|
LDL R2,#$0e
|
LDL R2,#$0e
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
LDL R6,#$34 ; Set offset to 4 and width to 3(4 bits)
|
LDL R6,#$34 ; Set offset to 4 and width to 3(4 bits)
|
LDL R5,#$a6 ; Set R5=$00a6
|
LDL R5,#$a6 ; Set R5=$00a6
|
LDH R5,#$c3 ; Set R5=$c3a6
|
LDH R5,#$c3 ; Set R5=$c3a6
|
| Line 795... |
Line 806... |
BFEXT R4,R5,R6 ; R4=$00c3
|
BFEXT R4,R5,R6 ; R4=$00c3
|
LDL R7,#$c3 ; R7=$00c3
|
LDL R7,#$c3 ; R7=$00c3
|
SUB R0,R7,R4 ; Compare R7 to R4
|
SUB R0,R7,R4 ; Compare R7 to R4
|
BNE _FAIL4
|
BNE _FAIL4
|
|
|
;Test BFINS instruction
|
;Test BFINS instruction *************************************************
|
LDL R2,#$06
|
LDL R2,#$06
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
LDL R6,#$34 ; Set offset to 4 and width to 3(4 bits)
|
LDL R6,#$34 ; Set offset to 4 and width to 3(4 bits)
|
LDL R5,#$a6 ; Set R5=$00a6
|
LDL R5,#$a6 ; Set R5=$00a6
|
LDH R5,#$c3 ; Set R5=$c3a6
|
LDH R5,#$c3 ; Set R5=$c3a6
|
| Line 820... |
Line 831... |
LDL R7,#$a6 ; R7=$00a6
|
LDL R7,#$a6 ; R7=$00a6
|
LDH R7,#$f3 ; R7=$f3a6
|
LDH R7,#$f3 ; R7=$f3a6
|
SUB R0,R7,R4 ; Compare R7 to R4
|
SUB R0,R7,R4 ; Compare R7 to R4
|
BNE _FAIL4
|
BNE _FAIL4
|
|
|
;Test BFINSI instruction
|
;Test BFINSI instruction ************************************************
|
LDL R2,#$06
|
LDL R2,#$06
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
LDL R6,#$3c ; Set offset to 12 and width to 3(4 bits)
|
LDL R6,#$3c ; Set offset to 12 and width to 3(4 bits)
|
LDL R5,#$a6 ; Set R5=$00a6
|
LDL R5,#$a6 ; Set R5=$00a6
|
LDH R5,#$c3 ; Set R5=$c3a6
|
LDH R5,#$c3 ; Set R5=$c3a6
|
| Line 845... |
Line 856... |
LDL R7,#$ff ; R7=$00ff
|
LDL R7,#$ff ; R7=$00ff
|
LDH R7,#$59 ; R7=$59ff
|
LDH R7,#$59 ; R7=$59ff
|
SUB R0,R7,R4 ; Compare R7 to R4
|
SUB R0,R7,R4 ; Compare R7 to R4
|
BNE _FAIL4
|
BNE _FAIL4
|
|
|
;Test BFINSX instruction
|
;Test BFINSX instruction ************************************************
|
LDL R2,#$06
|
LDL R2,#$06
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=1, Carry=0
|
LDL R6,#$38 ; Set offset to 8 and width to 3(4 bits)
|
LDL R6,#$38 ; Set offset to 8 and width to 3(4 bits)
|
LDL R5,#$a6 ; Set R5=$00a6
|
LDL R5,#$a6 ; Set R5=$00a6
|
LDH R5,#$c3 ; Set R5=$c3a6
|
LDH R5,#$c3 ; Set R5=$c3a6
|
| Line 901... |
Line 912... |
LDL R3,#$09 ; Checkpoint Value
|
LDL R3,#$09 ; Checkpoint Value
|
STB R3,(R2,#0)
|
STB R3,(R2,#0)
|
LDL R3,#$05 ; Thread Value
|
LDL R3,#$05 ; Thread Value
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
|
|
;Test BCC instruction C = 0
|
;Test BCC instruction C = 0 ******************************************
|
LDL R2,#$00
|
LDL R2,#$00
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
BCC _BCC_OK1 ; Take Branch
|
BCC _BCC_OK1 ; Take Branch
|
BRA _BR_ERR
|
BRA _BR_ERR
|
_BCC_OK1
|
_BCC_OK1
|
LDL R2,#$01
|
LDL R2,#$01
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
|
BCC _BR_ERR ; Don't take branch
|
BCC _BR_ERR ; Don't take branch
|
|
|
|
|
;Test BCS instruction C = 1
|
;Test BCS instruction C = 1 ******************************************
|
LDL R2,#$01
|
LDL R2,#$01
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
|
BCS _BCS_OK1 ; Take Branch
|
BCS _BCS_OK1 ; Take Branch
|
BRA _BR_ERR
|
BRA _BR_ERR
|
_BCS_OK1
|
_BCS_OK1
|
LDL R2,#$00
|
LDL R2,#$00
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
BCS _BR_ERR ; Don't take branch
|
BCS _BR_ERR ; Don't take branch
|
|
|
|
|
;Test BEQ instruction Z = 1
|
;Test BEQ instruction Z = 1 ******************************************
|
LDL R2,#$04
|
LDL R2,#$04
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
|
BEQ _BEQ_OK1 ; Take Branch
|
BEQ _BEQ_OK1 ; Take Branch
|
BRA _BR_ERR
|
BRA _BR_ERR
|
_BEQ_OK1
|
_BEQ_OK1
|
LDL R2,#$00
|
LDL R2,#$00
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
BEQ _BR_ERR ; Don't take branch
|
BEQ _BR_ERR ; Don't take branch
|
|
|
|
|
;Test BNE instruction Z = 0
|
;Test BNE instruction Z = 0 ******************************************
|
LDL R2,#$00
|
LDL R2,#$00
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
BNE _BNE_OK1 ; Take Branch
|
BNE _BNE_OK1 ; Take Branch
|
BRA _BR_ERR
|
BRA _BR_ERR
|
_BNE_OK1
|
_BNE_OK1
|
LDL R2,#$04
|
LDL R2,#$04
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
|
BNE _BR_ERR ; Don't take branch
|
BNE _BR_ERR ; Don't take branch
|
|
|
|
|
;Test BPL instruction N = 0
|
;Test BPL instruction N = 0 ******************************************
|
LDL R2,#$00
|
LDL R2,#$00
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
BPL _BPL_OK1 ; Take Branch
|
BPL _BPL_OK1 ; Take Branch
|
BRA _BR_ERR
|
BRA _BR_ERR
|
_BPL_OK1
|
_BPL_OK1
|
LDL R2,#$08
|
LDL R2,#$08
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
|
BPL _BR_ERR ; Don't take branch
|
BPL _BR_ERR ; Don't take branch
|
|
|
|
|
;Test BMI instruction N = 1
|
;Test BMI instruction N = 1 ******************************************
|
LDL R2,#$08
|
LDL R2,#$08
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
|
BMI _BMI_OK1 ; Take Branch
|
BMI _BMI_OK1 ; Take Branch
|
BRA _BR_ERR
|
BRA _BR_ERR
|
_BMI_OK1
|
_BMI_OK1
|
LDL R2,#$00
|
LDL R2,#$00
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
BMI _BR_ERR ; Don't take branch
|
BMI _BR_ERR ; Don't take branch
|
|
|
|
|
;Test BVC instruction V = 0
|
;Test BVC instruction V = 0 ******************************************
|
LDL R2,#$00
|
LDL R2,#$00
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
BVC _BVC_OK1 ; Take Branch
|
BVC _BVC_OK1 ; Take Branch
|
BRA _BR_ERR
|
BRA _BR_ERR
|
_BVC_OK1
|
_BVC_OK1
|
LDL R2,#$02
|
LDL R2,#$02
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
|
BVC _BR_ERR ; Don't take branch
|
BVC _BR_ERR ; Don't take branch
|
|
|
|
|
;Test BVS instruction V = 1
|
;Test BVS instruction V = 1 ******************************************
|
LDL R2,#$02
|
LDL R2,#$02
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
|
BVS _BVS_OK1 ; Take Branch
|
BVS _BVS_OK1 ; Take Branch
|
BRA _BR_ERR
|
BRA _BR_ERR
|
_BVS_OK1
|
_BVS_OK1
|
LDL R2,#$00
|
LDL R2,#$00
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
BVS _BR_ERR ; Don't take branch
|
BVS _BR_ERR ; Don't take branch
|
|
|
|
|
;Test BLS instruction C | Z = 1
|
;Test BLS instruction C | Z = 1 **************************************
|
LDL R2,#$01
|
LDL R2,#$01
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=1
|
BLS _BLS_OK1 ; Take Branch
|
BLS _BLS_OK1 ; Take Branch
|
BRA _BR_ERR
|
BRA _BR_ERR
|
_BLS_OK1
|
_BLS_OK1
|
| Line 1005... |
Line 1016... |
LDL R2,#$00
|
LDL R2,#$00
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
BLS _BR_ERR ; Don't take branch
|
BLS _BR_ERR ; Don't take branch
|
|
|
|
|
;Test BGE instruction N ^ V = 0
|
;Test BGE instruction N ^ V = 0 **************************************
|
LDL R2,#$0a
|
LDL R2,#$0a
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
BGE _BGE_OK1 ; Take Branch
|
BGE _BGE_OK1 ; Take Branch
|
BRA _BR_ERR
|
BRA _BR_ERR
|
_BGE_OK1
|
_BGE_OK1
|
| Line 1021... |
Line 1032... |
LDL R2,#$08
|
LDL R2,#$08
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
|
BGE _BR_ERR ; Don't take branch
|
BGE _BR_ERR ; Don't take branch
|
|
|
|
|
;Test BHI instruction Z | C = 0
|
;Test BLT instruction N ^ V = 1 **************************************
|
|
LDL R2,#$08
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
|
BLT _BLT_OK1 ; Take Branch
|
|
BRA _BR_ERR
|
|
_BLT_OK1
|
|
LDL R2,#$02
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=1
|
|
BLT _BLT_OK2 ; Take Branch
|
|
BRA _BR_ERR
|
|
_BLT_OK2
|
|
LDL R2,#$0a
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
|
BLT _BR_ERR ; Don't take branch
|
|
|
|
LDL R2,#$00
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
|
BLT _BR_ERR ; Don't take branch
|
|
|
|
|
|
;Test BHI instruction Z | C = 0 **************************************
|
LDL R2,#$0a
|
LDL R2,#$0a
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
BHI _BHI_OK1 ; Take Branch
|
BHI _BHI_OK1 ; Take Branch
|
BRA _BR_ERR
|
BRA _BR_ERR
|
_BHI_OK1
|
_BHI_OK1
|
| Line 1036... |
Line 1067... |
LDL R2,#$0e
|
LDL R2,#$0e
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
BHI _BR_ERR ; Don't take branch
|
BHI _BR_ERR ; Don't take branch
|
|
|
|
|
;Test BGT instruction Z | (N ^ V) = 0
|
;Test BGT instruction Z | (N ^ V) = 0 ********************************
|
LDL R2,#$0a
|
LDL R2,#$0a
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
BGT _BGT_OK1 ; Take Branch
|
BGT _BGT_OK1 ; Take Branch
|
BRA _BR_ERR
|
BRA _BR_ERR
|
_BGT_OK1
|
_BGT_OK1
|
| Line 1060... |
Line 1091... |
LDL R2,#$08
|
LDL R2,#$08
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
|
BGT _BR_ERR ; Don't take branch
|
BGT _BR_ERR ; Don't take branch
|
|
|
|
|
|
;Test BLE instruction Z | (N ^ V) = 1 ********************************
|
|
LDL R2,#$04
|
|
TFR CCR,R2 ; Negative=0, Zero=1, Overflow=0, Carry=0
|
|
BLE _BLE_OK1 ; Take Branch
|
|
BRA _BR_ERR
|
|
_BLE_OK1
|
|
LDL R2,#$02
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=1, Carry=0
|
|
BLE _BLE_OK2 ; Take Branch
|
|
BRA _BR_ERR
|
|
_BLE_OK2
|
|
LDL R2,#$08
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=0, Carry=0
|
|
BLE _BLE_OK3 ; Take Branch
|
|
BRA _BR_ERR
|
|
_BLE_OK3
|
|
LDL R2,#$0a
|
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=0
|
|
BLE _BR_ERR ; Don't take branch
|
|
|
|
LDL R2,#$00
|
|
TFR CCR,R2 ; Negative=0, Zero=0, Overflow=0, Carry=0
|
|
BLE _BR_ERR ; Don't take branch
|
|
|
|
|
|
;Test BRA instruction **************************************************
|
BRA BRA_FWARD
|
BRA BRA_FWARD
|
|
|
|
|
_BR_ERR
|
_BR_ERR
|
LDL R2,#$04 ; Sent Message to Testbench Error Register
|
LDL R2,#$04 ; Sent Message to Testbench Error Register
|
| Line 1139... |
Line 1196... |
LDL R3,#$0d ; Checkpoint Value
|
LDL R3,#$0d ; Checkpoint Value
|
STB R3,(R2,#0)
|
STB R3,(R2,#0)
|
LDL R3,#$07 ; Thread Value
|
LDL R3,#$07 ; Thread Value
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
|
|
;Test SUB instruction
|
;Test SUB instruction ***************************************************
|
LDL R4,#$0f ; R4=$000f
|
LDL R4,#$0f ; R4=$000f
|
LDH R4,#$01 ; R4=$010f
|
LDH R4,#$01 ; R4=$010f
|
LDL R7,#$0e ; R7=$000e
|
LDL R7,#$0e ; R7=$000e
|
LDH R7,#$01 ; R7=$010e
|
LDH R7,#$01 ; R7=$010e
|
LDL R2,#$0f
|
LDL R2,#$0f
|
| Line 1166... |
Line 1223... |
BNE _FAIL7 ; Zero Flag should be set
|
BNE _FAIL7 ; Zero Flag should be set
|
BVS _FAIL7 ; Overflow Flag should be clear
|
BVS _FAIL7 ; Overflow Flag should be clear
|
BCS _FAIL7 ; Carry Flag should be clear
|
BCS _FAIL7 ; Carry Flag should be clear
|
|
|
|
|
;Test SBC instruction
|
;Test SBC instruction ***************************************************
|
LDL R4,#$11 ; R4=$0011
|
LDL R4,#$11 ; R4=$0011
|
LDH R4,#$01 ; R4=$0111
|
LDH R4,#$01 ; R4=$0111
|
LDL R7,#$0e ; R7=$000e
|
LDL R7,#$0e ; R7=$000e
|
LDH R7,#$01 ; R7=$010e
|
LDH R7,#$01 ; R7=$010e
|
LDL R2,#$0f
|
LDL R2,#$0f
|
| Line 1195... |
Line 1252... |
BEQ _FAIL7 ; Zero Flag should be clear
|
BEQ _FAIL7 ; Zero Flag should be clear
|
BVS _FAIL7 ; Overflow Flag should be clear
|
BVS _FAIL7 ; Overflow Flag should be clear
|
BCS _FAIL7 ; Carry Flag should be clear
|
BCS _FAIL7 ; Carry Flag should be clear
|
|
|
|
|
;Test ADD instruction
|
;Test ADD instruction ***************************************************
|
LDL R4,#$0f ; R4=$000f
|
LDL R4,#$0f ; R4=$000f
|
LDH R4,#$70 ; R4=$700f
|
LDH R4,#$70 ; R4=$700f
|
LDL R7,#$01 ; R7=$0001
|
LDL R7,#$01 ; R7=$0001
|
LDH R7,#$10 ; R7=$1001
|
LDH R7,#$10 ; R7=$1001
|
LDL R2,#$05
|
LDL R2,#$05
|
| Line 1227... |
Line 1284... |
BCC _FAIL7 ; Carry Flag should be set
|
BCC _FAIL7 ; Carry Flag should be set
|
SUB R0,R1,R0 ; Compare R1 to R0(Zero)
|
SUB R0,R1,R0 ; Compare R1 to R0(Zero)
|
BNE _FAIL7
|
BNE _FAIL7
|
|
|
|
|
;Test ADC instruction
|
;Test ADC instruction ***************************************************
|
LDL R4,#$0f ; R4=$000f
|
LDL R4,#$0f ; R4=$000f
|
LDH R4,#$70 ; R4=$700f
|
LDH R4,#$70 ; R4=$700f
|
LDL R7,#$01 ; R7=$0001
|
LDL R7,#$01 ; R7=$0001
|
LDH R7,#$10 ; R7=$1001
|
LDH R7,#$10 ; R7=$1001
|
LDL R2,#$05
|
LDL R2,#$05
|
| Line 1288... |
Line 1345... |
LDL R3,#$0f ; Checkpoint Value
|
LDL R3,#$0f ; Checkpoint Value
|
STB R3,(R2,#0)
|
STB R3,(R2,#0)
|
LDL R3,#$08 ; Thread Value
|
LDL R3,#$08 ; Thread Value
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
|
|
;Test SUBL instruction
|
;Test SUBL instruction **************************************************
|
LDL R5,#$0f ; R5=$000f
|
LDL R5,#$0f ; R5=$000f
|
LDL R2,#$0f
|
LDL R2,#$0f
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
|
SUBL R5,#$0e ; R5 - $0e => R5
|
SUBL R5,#$0e ; R5 - $0e => R5
|
BMI _FAIL8 ; Negative Flag should be clear
|
BMI _FAIL8 ; Negative Flag should be clear
|
| Line 1313... |
Line 1370... |
BCC _FAIL8 ; Carry Flag should be set
|
BCC _FAIL8 ; Carry Flag should be set
|
CMPL R7,#$FF ; Result should be -1 or $FFFF
|
CMPL R7,#$FF ; Result should be -1 or $FFFF
|
CPCH R7,#$FF
|
CPCH R7,#$FF
|
BNE _FAIL8
|
BNE _FAIL8
|
|
|
;Test SUBH instruction
|
;Test SUBH instruction **************************************************
|
LDL R6,#$11 ; R4=$0011
|
LDL R6,#$11 ; R4=$0011
|
LDH R6,#$81 ; R4=$8111
|
LDH R6,#$81 ; R4=$8111
|
LDL R2,#$0d
|
LDL R2,#$0d
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=1
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=0, Carry=1
|
SUBH R6,#$70 ; R6 - $70 => R6
|
SUBH R6,#$70 ; R6 - $70 => R6
|
| Line 1339... |
Line 1396... |
BEQ _FAIL8 ; Zero Flag should be clear
|
BEQ _FAIL8 ; Zero Flag should be clear
|
BVS _FAIL8 ; Overflow Flag should be clear
|
BVS _FAIL8 ; Overflow Flag should be clear
|
BCC _FAIL8 ; Carry Flag should be set
|
BCC _FAIL8 ; Carry Flag should be set
|
|
|
|
|
;Test CMPL instruction
|
;Test CMPL instruction **************************************************
|
LDL R5,#$0f ; R5=$000f
|
LDL R5,#$0f ; R5=$000f
|
LDL R2,#$0b
|
LDL R2,#$0b
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
TFR CCR,R2 ; Negative=1, Zero=0, Overflow=1, Carry=1
|
CMPL R5,#$0f ; R5 - $0f => R5
|
CMPL R5,#$0f ; R5 - $0f => R5
|
BMI _FAIL8 ; Negative Flag should be clear
|
BMI _FAIL8 ; Negative Flag should be clear
|
| Line 1359... |
Line 1416... |
BEQ _FAIL8 ; Zero Flag should be clear
|
BEQ _FAIL8 ; Zero Flag should be clear
|
BVS _FAIL8 ; Overflow Flag should be clear
|
BVS _FAIL8 ; Overflow Flag should be clear
|
BCC _FAIL8 ; Carry Flag should be set
|
BCC _FAIL8 ; Carry Flag should be set
|
|
|
|
|
;Test CPCH instruction
|
;Test CPCH instruction **************************************************
|
LDL R5,#$00 ; R5=$0000
|
LDL R5,#$00 ; R5=$0000
|
LDH R5,#$01 ; R5=$0001
|
LDH R5,#$01 ; R5=$0001
|
LDL R2,#$0f
|
LDL R2,#$0f
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=1
|
CPCH R5,#$00 ; R5 - $00 - carryflag => nowhere
|
CPCH R5,#$00 ; R5 - $00 - carryflag => nowhere
|
| Line 1378... |
Line 1435... |
BEQ _FAIL8 ; Zero Flag should be clear
|
BEQ _FAIL8 ; Zero Flag should be clear
|
BVS _FAIL8 ; Overflow Flag should be clear
|
BVS _FAIL8 ; Overflow Flag should be clear
|
BCC _FAIL8 ; Carry Flag should be set
|
BCC _FAIL8 ; Carry Flag should be set
|
|
|
|
|
;Test ADDH instruction
|
;Test ADDH instruction **************************************************
|
LDL R5,#$0f ; R5=$000f
|
LDL R5,#$0f ; R5=$000f
|
LDH R5,#$70 ; R5=$700f
|
LDH R5,#$70 ; R5=$700f
|
LDL R2,#$0e
|
LDL R2,#$0e
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
ADDH R5,#$a0 ; R5 + $a0 => R5
|
ADDH R5,#$a0 ; R5 + $a0 => R5
|
| Line 1406... |
Line 1463... |
LDH R3,#$80 ; R3=$800f
|
LDH R3,#$80 ; R3=$800f
|
SUB R0,R5,R3 ; Compare R5 to R3
|
SUB R0,R5,R3 ; Compare R5 to R3
|
BNE _FAIL8
|
BNE _FAIL8
|
|
|
|
|
;Test ADDL instruction
|
;Test ADDL instruction **************************************************
|
LDL R4,#$ff ; R4=$00ff
|
LDL R4,#$ff ; R4=$00ff
|
LDH R4,#$70 ; R4=$70ff
|
LDH R4,#$70 ; R4=$70ff
|
LDL R2,#$0e
|
LDL R2,#$0e
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
TFR CCR,R2 ; Negative=1, Zero=1, Overflow=1, Carry=0
|
ADDL R4,#$01 ; R4 + $01 => R4
|
ADDL R4,#$01 ; R4 + $01 => R4
|
| Line 1475... |
Line 1532... |
LDL R3,#$66 ; R3=$0066
|
LDL R3,#$66 ; R3=$0066
|
LDH R3,#$5f ; R3=$5f66
|
LDH R3,#$5f ; R3=$5f66
|
LDL R7,#$ff ; R7=$00ff
|
LDL R7,#$ff ; R7=$00ff
|
LDH R7,#$ff ; R7=$ffff
|
LDH R7,#$ff ; R7=$ffff
|
|
|
;Test STB/LDB instruction
|
;Test STB/LDB instruction ***********************************************
|
STB R1,(R0,#$00) ;
|
STB R1,(R0,#$00) ;
|
STB R2,(R0,#$01) ;
|
STB R2,(R0,#$01) ;
|
STB R3,(R0,#$1f) ;
|
STB R3,(R0,#$1f) ;
|
LDL R4,#$00 ; R4=$0000
|
LDL R4,#$00 ; R4=$0000
|
LDB R5,(R4,#$00) ;
|
LDB R5,(R4,#$00) ;
|
| Line 1493... |
Line 1550... |
BNE _FAIL9
|
BNE _FAIL9
|
LDL R6,#$66 ; R6=$0066
|
LDL R6,#$66 ; R6=$0066
|
CMP R6,R7 ; Make sure the high byte has been cleared
|
CMP R6,R7 ; Make sure the high byte has been cleared
|
BNE _FAIL9
|
BNE _FAIL9
|
|
|
;Test STW/LDW instruction
|
;Test STW/LDW instruction ***********************************************
|
STW R1,(R0,#$04) ; Should be even offsets
|
STW R1,(R0,#$04) ; Should be even offsets
|
STW R2,(R0,#$06) ;
|
STW R2,(R0,#$06) ;
|
STW R3,(R0,#$0a) ;
|
STW R3,(R0,#$0a) ;
|
LDL R4,#$00 ; R4=$0000
|
LDL R4,#$00 ; R4=$0000
|
LDL R5,#$00 ; R5=$0000
|
LDL R5,#$00 ; R5=$0000
|
| Line 1511... |
Line 1568... |
CMP R2,R6 ;
|
CMP R2,R6 ;
|
BNE _FAIL9
|
BNE _FAIL9
|
CMP R3,R7 ;
|
CMP R3,R7 ;
|
BNE _FAIL9
|
BNE _FAIL9
|
|
|
;Test STB/LDB instruction
|
;Test STB/LDB instruction ***********************************************
|
LDL R1,#$cc ; R1=$00cc
|
LDL R1,#$cc ; R1=$00cc
|
LDH R1,#$1f ; R1=$1f66
|
LDH R1,#$1f ; R1=$1f66
|
LDL R2,#$99 ; R2=$0099
|
LDL R2,#$99 ; R2=$0099
|
LDH R2,#$2f ; R2=$2f99
|
LDH R2,#$2f ; R2=$2f99
|
|
|
| Line 1530... |
Line 1587... |
BNE _FAIL9
|
BNE _FAIL9
|
LDL R3,#$99 ; R3=$0099
|
LDL R3,#$99 ; R3=$0099
|
CMP R3,R6 ; Make sure the high byte has been cleared
|
CMP R3,R6 ; Make sure the high byte has been cleared
|
BNE _FAIL9
|
BNE _FAIL9
|
|
|
;Test STW/LDW instruction
|
;Test STW/LDW instruction ***********************************************
|
LDL R1,#$cc ; R1=$00cc
|
LDL R1,#$cc ; R1=$00cc
|
LDH R1,#$1f ; R1=$1f66
|
LDH R1,#$1f ; R1=$1f66
|
LDL R2,#$99 ; R2=$0099
|
LDL R2,#$99 ; R2=$0099
|
LDH R2,#$2f ; R2=$2f99
|
LDH R2,#$2f ; R2=$2f99
|
|
|
| Line 1548... |
Line 1605... |
CMP R5,R1 ;
|
CMP R5,R1 ;
|
BNE _FAIL9
|
BNE _FAIL9
|
CMP R6,R2 ;
|
CMP R6,R2 ;
|
BNE _FAIL9
|
BNE _FAIL9
|
|
|
;Test STB/LDB instruction
|
;Test STB/LDB instruction ***********************************************
|
LDL R1,#$33 ; R1=$0033
|
LDL R1,#$33 ; R1=$0033
|
LDH R1,#$1f ; R1=$1f33
|
LDH R1,#$1f ; R1=$1f33
|
LDL R2,#$55 ; R2=$0055
|
LDL R2,#$55 ; R2=$0055
|
LDH R2,#$2f ; R2=$2f55
|
LDH R2,#$2f ; R2=$2f55
|
|
|
| Line 1575... |
Line 1632... |
BNE _FAIL9
|
BNE _FAIL9
|
LDL R3,#$55 ; R3=$0055
|
LDL R3,#$55 ; R3=$0055
|
CMP R3,R7 ; Make sure the high byte has been cleared
|
CMP R3,R7 ; Make sure the high byte has been cleared
|
BNE _FAIL9
|
BNE _FAIL9
|
|
|
;Test STB/LDB instruction
|
;Test STB/LDB instruction ***********************************************
|
LDL R1,#$66 ; R1=$0066
|
LDL R1,#$66 ; R1=$0066
|
LDH R1,#$1f ; R1=$1f66
|
LDH R1,#$1f ; R1=$1f66
|
LDL R2,#$99 ; R2=$0099
|
LDL R2,#$99 ; R2=$0099
|
LDH R2,#$2f ; R2=$2f99
|
LDH R2,#$2f ; R2=$2f99
|
|
|
| Line 1602... |
Line 1659... |
BNE _FAIL9
|
BNE _FAIL9
|
LDL R3,#$99 ; R3=$0099
|
LDL R3,#$99 ; R3=$0099
|
CMP R3,R7 ; Make sure the high byte has been cleared
|
CMP R3,R7 ; Make sure the high byte has been cleared
|
BNE _FAIL9
|
BNE _FAIL9
|
|
|
;Test STW/LDW instruction
|
;Test STW/LDW instruction ***********************************************
|
LDL R1,#$aa ; R1=$00aa
|
LDL R1,#$aa ; R1=$00aa
|
LDH R1,#$1f ; R1=$1faa
|
LDH R1,#$1f ; R1=$1faa
|
LDL R2,#$cc ; R2=$00cc
|
LDL R2,#$cc ; R2=$00cc
|
LDH R2,#$2f ; R2=$2fcc
|
LDH R2,#$2f ; R2=$2fcc
|
|
|
| Line 1628... |
Line 1685... |
CMP R1,R3 ;
|
CMP R1,R3 ;
|
BNE _FAIL9
|
BNE _FAIL9
|
CMP R2,R7 ;
|
CMP R2,R7 ;
|
BNE _FAIL9
|
BNE _FAIL9
|
|
|
|
;Test STW/LDW instruction ***********************************************
|
|
LDL R1,#$66 ; R1=$0066
|
|
LDH R1,#$99 ; R1=$9966
|
|
LDL R2,#$33 ; R2=$0033
|
|
LDH R2,#$75 ; R2=$7533
|
|
|
|
LDL R4,#$80 ; R4=$0080 - Base Address
|
|
LDL R5,#$02 ; R5=$0002 - even offset
|
|
LDL R6,#$08 ; R6=$0008
|
|
STW R1,(R4,-R5) ;
|
|
STW R2,(R4,-R6) ;
|
|
CMPL R5,#$00 ; Test for 2 byte increment
|
|
BNE _FAIL9
|
|
CMPL R6,#$06 ; Test for 2 byte increment
|
|
BNE _FAIL9
|
|
LDW R3,(R4,R5+) ;
|
|
LDW R7,(R4,R6+) ;
|
|
CMPL R5,#$02 ; Test for 2 byte decrement
|
|
BNE _FAIL9
|
|
CMPL R6,#$08 ; Test for 2 byte decrement
|
|
BNE _FAIL9
|
|
CMP R1,R3 ;
|
|
BNE _FAIL9
|
|
CMP R2,R7 ;
|
|
BNE _FAIL9
|
|
|
_END_9
|
_END_9
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
LDL R2,#$00 ; Sent Message to Testbench Check Point Register
|
LDH R2,#$80
|
LDH R2,#$80
|
LDL R3,#$12
|
LDL R3,#$12
|
STB R3,(R2,#0)
|
STB R3,(R2,#0)
|
| Line 1660... |
Line 1743... |
LDL R3,#$0a ; Thread Value
|
LDL R3,#$0a ; Thread Value
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
STB R3,(R2,#2) ; Send Message to clear Testbench interrupt register
|
|
|
LDL R1,#$5 ; R1=$0005
|
LDL R1,#$5 ; R1=$0005
|
|
|
;Test SSEM instruction
|
;Test SSEM instruction **************************************************
|
SSEM #7 ; semaphores
|
SSEM #7 ; semaphores
|
BCC _FAIL10 ; Should be set
|
BCC _FAIL10 ; Should be set
|
SSEM R1 ; semaphores
|
SSEM R1 ; semaphores
|
BCC _FAIL10 ; Should be set
|
BCC _FAIL10 ; Should be set
|
|
|
| Line 1698... |
Line 1781... |
|
|
|
|
;-------------------------------------------------------------------------------
|
;-------------------------------------------------------------------------------
|
;-------------------------------------------------------------------------------
|
;-------------------------------------------------------------------------------
|
|
|
TFR R2,CCR ; R2 = CCR
|
|
|
|
;empty line
|
;empty line
|
|
|
BACK_
|
BACK_
|
|
|
