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10GE MAC Core
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========================
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1. Directory Structure
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The directory structure for this project is shown below.
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.
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|-- doc - Documentation files
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|-- rtl
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| |-- include - Verilog defines and utils
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| `-- verilog - Verilog source files for xge_mac
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|-- sim
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| |-- systemc - SystemC simulation directory
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| `-- verilog - Verilog simulation directory
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`-- tbench
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|-- systemc - SystemC test-bench source files
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`-- verilog - Verilog test-bench source files
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2. Simulation
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There are two simulation environments that can be used to validate the code.
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The verilog simulation is very basic and meant for those who want to look
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at how the MAC operates without going through the effort of setting up SystemC.
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The SystemC environment is more sophisticated and covers all features of the MAC.
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2.1 Verilog Simulation
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------------------------
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To run the verilog simulation, compile all project files under rtl/verilog along with
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top level testbench file:
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- tbench/verilog/tb_xge_mac.v
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There is a Modelsim "do" file called "sim.do" under sim/verilog for those using Modelsim.
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Once all the files are compiled, start simulation using entity "tb".
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The verilog simulation reads packets from "packet_tx.txt" and writes them to the MAC
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transmit fifo using the packet transmit interface (pkt_tx_data). As frames become
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available in the transmit fifo, the MAC calulates the CRC and sends them out on xgmii_tx.
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The xgmii_tx interface is looped-back to xgmii_rx in the testbench. The frames are thus
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processed by the MAC receive engine and stored in the receive fifo. The testbench reads
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frames from the receive interface (pkt_rx_data) and prints out the results.
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2.2 SystemC Simulation
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In order to use the SystemC environment it is required to first install SystemC from
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www.systemc.org. Free membership may be required to download the core SystemC files.
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The testbench was developed and tested with Verilator, a free HDL simulator that
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compiles verilog into C++ or SystemC code. You can download Verilator from
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www.veripool.org. You also need to install SystemPerl and Verilog-Perl for waveform
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traces.
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Once all the required tools are installed:
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- Move to directory sim/systemc
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- Type "./compile.sh"
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- Type "./run.sh"
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If the simulation is running correctly you should see messages from the scoreboard
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as packets are transmited and received on the various interfaces.
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Simulation output:
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Packet size
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SCOREBOARD XGMII INTERFACE TX (60)
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SCOREBOARD XGMII INTERFACE TX (60)
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SCOREBOARD PACKET INTERFACE TX (50)
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SCOREBOARD XGMII INTERFACE TX (60)
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SCOREBOARD PACKET INTERFACE TX (51)
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SCOREBOARD XGMII INTERFACE TX (60)
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SCOREBOARD PACKET INTERFACE RX (TX SIZE=60 RX SIZE=60)
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...
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