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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [fault_sm.v] - Diff between revs 7 and 12
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| Rev 7 |
Rev 12 |
| Line 71... |
Line 71... |
reg [1:0] seq_type;
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reg [1:0] seq_type;
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reg [1:0] seq_add;
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reg [1:0] seq_add;
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// End of automatics
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parameter [1:0]
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parameter [1:0]
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SM_INIT = 2'd0,
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SM_INIT = 2'd0,
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SM_COUNT = 2'd1,
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SM_COUNT = 2'd1,
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