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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_mem_medium.v] - Diff between revs 7 and 20

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Rev 7	Rev 20
Line 57...	Line 57...
`// Parameters`	`// Parameters`

`parameter DWIDTH = 32;`	`parameter DWIDTH = 32;`
`parameter AWIDTH = 3;`	`parameter AWIDTH = 3;`
`parameter RAM_DEPTH = (1 << AWIDTH);`	`parameter RAM_DEPTH = (1 << AWIDTH);`
`parameter SYNC_WRITE = 1;`
`parameter SYNC_READ = 1;`
`parameter REGISTER_READ = 0;`	`parameter REGISTER_READ = 0;`

`//---`	`//---`
`// Ports`	`// Ports`

`input wclk;`	`input wclk;`
`input wrst_n;`	`input wrst_n;`
`input wen;`	`input wen;`
`input [AWIDTH:0] waddr;`	`input [AWIDTH-1:0] waddr;`
`input [DWIDTH-1:0] wdata;`	`input [DWIDTH-1:0] wdata;`

`input rclk;`	`input rclk;`
`input rrst_n;`	`input rrst_n;`
`input ren;`	`input ren;`
`input roen;`	`input roen;`
`input [AWIDTH:0] raddr;`	`input [AWIDTH-1:0] raddr;`
`output [DWIDTH-1:0] rdata;`	`output [DWIDTH-1:0] rdata;`

`// Registered outputs`	`// Registered outputs`
`reg [DWIDTH-1:0] rdata;`	`reg [DWIDTH-1:0] rdata;`

Line 101...	Line 99...


`//---`	`//---`
`// Memory Write`	`// Memory Write`

`generate`
`if (SYNC_WRITE) begin`

`// Generate synchronous write`	`// Generate synchronous write`
`always @(posedge wclk)`	`always @(posedge wclk)`
`begin`	`begin`
`if (wen) begin`	`if (wen) begin`
`mem[waddr[AWIDTH-1:0]] <= wdata;`	`mem[waddr[AWIDTH-1:0]] <= wdata;`
`end`	`end`
`end`	`end`
`end`
`else begin`

`// Generate asynchronous write`
`always @(wen, waddr, wdata)`
`begin`
`if (wen) begin`
`mem[waddr[AWIDTH-1:0]] = wdata;`
`end`
`end`
`end`
`endgenerate`

`//---`	`//---`
`// Memory Read`	`// Memory Read`

`generate`
`if (SYNC_READ) begin`

`// Generate registered memory read`	`// Generate registered memory read`
`always @(posedge rclk or negedge rrst_n)`	`always @(posedge rclk or negedge rrst_n)`
`begin`	`begin`
`if (!rrst_n) begin`	`if (!rrst_n) begin`
`mem_rdata <= {(DWIDTH){1'b0}};`	`mem_rdata <= {(DWIDTH){1'b0}};`
`end else if (ren) begin`	`end else if (ren) begin`
`mem_rdata <= mem[raddr[AWIDTH-1:0]];`	`mem_rdata <= mem[raddr[AWIDTH-1:0]];`
`end`	`end`
`end`	`end`
`end`
`else begin`

`// Generate unregisters memory read`
`always @(raddr, rclk)`
`begin`
`mem_rdata = mem[raddr[AWIDTH-1:0]];`
`end`
`end`
`endgenerate`

`generate`	`generate`
`if (REGISTER_READ) begin`	`if (REGISTER_READ) begin`

`// Generate registered output`	`// Generate registered output`
Line 177...	Line 147...
`end`	`end`
`endgenerate`	`endgenerate`

`endmodule`	`endmodule`




`No newline at end of file`	`No newline at end of file`

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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_mem_medium.v] - Diff between revs 7 and 20