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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_mem_small.v] - Diff between revs 20 and 21

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Rev 20 Rev 21
Line 85... Line 85...
// Local declarations
// Local declarations
 
 
// Registers
// Registers
 
 
reg  [DWIDTH-1:0] mem_rdata;
reg  [DWIDTH-1:0] mem_rdata;
 
reg  [AWIDTH-1:0] raddr_d1;
 
 
 
 
// Memory
// Memory
 
 
reg  [DWIDTH-1:0] mem [0:RAM_DEPTH-1];
reg  [DWIDTH-1:0] mem [0:RAM_DEPTH-1];
Line 111... Line 112...
 
 
//---
//---
// Memory Read
// Memory Read
 
 
// Generate registered memory read
// Generate registered memory read
 
 
 
`ifdef XIL
 
 
 
//always @(posedge rclk)
 
//begin
 
//    if (ren) begin
 
//        raddr_d1 <= raddr;
 
//    end
 
//end
 
//always @(raddr_d1, rclk)
 
//begin
 
//    mem_rdata = mem[raddr_d1[AWIDTH-1:0]];
 
//end
 
 
 
always @(posedge rclk)
 
begin
 
    if (!rrst_n) begin
 
        mem_rdata <= {(DWIDTH){1'b0}};
 
    end else if (ren) begin
 
        mem_rdata <= mem[raddr[AWIDTH-1:0]];
 
    end
 
end
 
 
 
`else
 
 
always @(posedge rclk or negedge rrst_n)
always @(posedge rclk or negedge rrst_n)
begin
begin
    if (!rrst_n) begin
    if (!rrst_n) begin
        mem_rdata <= {(DWIDTH){1'b0}};
        mem_rdata <= {(DWIDTH){1'b0}};
    end else if (ren) begin
    end else if (ren) begin
        mem_rdata <= mem[raddr[AWIDTH-1:0]];
        mem_rdata <= mem[raddr[AWIDTH-1:0]];
    end
    end
end
end
 
 
 
`endif
 
 
generate
generate
    if (REGISTER_READ) begin
    if (REGISTER_READ) begin
 
 
        // Generate registered output
        // Generate registered output
        always @(posedge rclk or negedge rrst_n)
        always @(posedge rclk or negedge rrst_n)

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