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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [generic_mem_small.v] - Diff between revs 22 and 25

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Rev 22 Rev 25
Line 139... Line 139...
    end
    end
end
end
 
 
`else
`else
 
 
always @(posedge rclk or negedge rrst_n)
//always @(posedge rclk or negedge rrst_n)
 
//begin
 
//    if (!rrst_n) begin
 
//        mem_rdata <= {(DWIDTH){1'b0}};
 
//    end else if (ren) begin
 
//        mem_rdata <= mem[raddr[AWIDTH-1:0]];
 
//    end
 
//end
 
 
 
always @(posedge rclk)
begin
begin
    if (!rrst_n) begin
    if (ren) begin
        mem_rdata <= {(DWIDTH){1'b0}};
        raddr_d1 <= raddr;
    end else if (ren) begin
    end
        mem_rdata <= mem[raddr[AWIDTH-1:0]];
 
    end
    end
 
always @(raddr_d1, rclk)
 
begin
 
    mem_rdata = mem[raddr_d1[AWIDTH-1:0]];
end
end
 
 
`endif
`endif
 
 
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