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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [rx_enqueue.v] - Diff between revs 12 and 21

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Rev 12 Rev 21
Line 169... Line 169... 
 
 
 
 
parameter [2:0]
 
parameter [2:0]
 
             SM_IDLE = 3'd0,
 
             SM_IDLE = 3'd0,
 
             SM_RX = 3'd1;
 
             SM_RX = 3'd1;
 
 
 
 
 
 
 
// count the number of set bits in a nibble
 
 
 
function [2:0] bit_cnt4;
 
 
 
input   [3:0]   bits;
 
 
 
    begin
 
 
 
    case (bits)
 
 
 
    0:  bit_cnt4 = 0;
 
 
 
    1:  bit_cnt4 = 1;
 
 
 
    2:  bit_cnt4 = 1;
 
 
 
    3:  bit_cnt4 = 2;
 
 
 
    4:  bit_cnt4 = 1;
 
 
 
    5:  bit_cnt4 = 2;
 
 
 
    6:  bit_cnt4 = 2;
 
 
 
    7:  bit_cnt4 = 3;
 
 
 
    8:  bit_cnt4 = 1;
 
 
 
    9:  bit_cnt4 = 2;
 
 
 
    10: bit_cnt4 = 2;
 
 
 
    11: bit_cnt4 = 3;
 
 
 
    12: bit_cnt4 = 2;
 
 
 
    13: bit_cnt4 = 3;
 
 
 
    14: bit_cnt4 = 3;
 
 
 
    15: bit_cnt4 = 4;
 
 
 
    endcase
 
 
 
    end
 
 
 
endfunction
 
 
 
 
 
 
 
function [3:0] bit_cnt8;
 
 
 
input   [7:0]   bits;
 
 
 
    begin
 
 
 
    bit_cnt8 = bit_cnt4(bits[3:0]) + bit_cnt4(bits[7:4]);
 
 
 
    end
 
 
 
endfunction
 
 
 
 
 
always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin
 
always @(posedge clk_xgmii_rx or negedge reset_xgmii_rx_n) begin
 
 
 
 
 
    if (reset_xgmii_rx_n == 1'b0) begin
 
    if (reset_xgmii_rx_n == 1'b0) begin
 
 
 
 
 
        xgmii_rxd_d1 <= 32'b0;
 
        xgmii_rxd_d1 <= 32'b0;
Line 539... Line 571... 
                  if (curr_byte_cnt == 14'b0) begin
 
                  if (curr_byte_cnt == 14'b0) begin
 
                      rxhfifo_wstatus[`RXSTATUS_SOP] = 1'b1;
 
                      rxhfifo_wstatus[`RXSTATUS_SOP] = 1'b1;
 
                  end
 
                  end
 
 
 
 
 
                  /* verilator lint_off WIDTH */
 
                  /* verilator lint_off WIDTH */
 
                  next_byte_cnt = curr_byte_cnt +
 
                  //next_byte_cnt = curr_byte_cnt +
 
                                  addmask[0] + addmask[1] + addmask[2] + addmask[3] +
 
                  //                addmask[0] + addmask[1] + addmask[2] + addmask[3] +
 
                                  addmask[4] + addmask[5] + addmask[6] + addmask[7];
 
                  //                addmask[4] + addmask[5] + addmask[6] + addmask[7];
 
                  /* verilator lint_on WIDTH */
 
                  /* verilator lint_on WIDTH */
 
 
 
                  // don't infer a chain of adders
 
 
 
                  next_byte_cnt = curr_byte_cnt + {10'b0, bit_cnt8(addmask[7:0])};
 
 
 
 
 
 
 
 
 
                  // We will not write to the fifo if all is left
 
                  // We will not write to the fifo if all is left
 
                  // are four or less bytes of crc. We also strip off the
 
                  // are four or less bytes of crc. We also strip off the
 
                  // crc, which requires looking one cycle ahead
 
                  // crc, which requires looking one cycle ahead
Line 758... Line 791... 
 
 
 
 
end
 
end
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
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