| Line 42... |
Line 42... |
// Outputs
|
// Outputs
|
rxdfifo_wdata, rxdfifo_wstatus, rxdfifo_wen, rxhfifo_ren,
|
rxdfifo_wdata, rxdfifo_wstatus, rxdfifo_wen, rxhfifo_ren,
|
rxhfifo_wdata, rxhfifo_wstatus, rxhfifo_wen, local_fault_msg_det,
|
rxhfifo_wdata, rxhfifo_wstatus, rxhfifo_wen, local_fault_msg_det,
|
remote_fault_msg_det, status_crc_error_tog,
|
remote_fault_msg_det, status_crc_error_tog,
|
status_fragment_error_tog, status_rxdfifo_ovflow_tog,
|
status_fragment_error_tog, status_rxdfifo_ovflow_tog,
|
status_pause_frame_rx_tog,
|
status_pause_frame_rx_tog, status_good_frame_rx_tog,
|
|
status_good_frame_rx_size,
|
// Inputs
|
// Inputs
|
clk_xgmii_rx, reset_xgmii_rx_n, xgmii_rxd, xgmii_rxc, rxdfifo_wfull,
|
clk_xgmii_rx, reset_xgmii_rx_n, xgmii_rxd, xgmii_rxc, rxdfifo_wfull,
|
rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty,
|
rxhfifo_rdata, rxhfifo_rstatus, rxhfifo_rempty,
|
rxhfifo_ralmost_empty
|
rxhfifo_ralmost_empty
|
);
|
);
|
| Line 85... |
Line 86... |
output status_fragment_error_tog;
|
output status_fragment_error_tog;
|
output status_rxdfifo_ovflow_tog;
|
output status_rxdfifo_ovflow_tog;
|
|
|
output status_pause_frame_rx_tog;
|
output status_pause_frame_rx_tog;
|
|
|
|
output status_good_frame_rx_tog;
|
|
output [13:0] status_good_frame_rx_size;
|
|
|
|
|
|
|
|
|
/*AUTOREG*/
|
/*AUTOREG*/
|
// Beginning of automatic regs (for this module's undeclared outputs)
|
// Beginning of automatic regs (for this module's undeclared outputs)
|
| Line 101... |
Line 105... |
reg [63:0] rxhfifo_wdata;
|
reg [63:0] rxhfifo_wdata;
|
reg rxhfifo_wen;
|
reg rxhfifo_wen;
|
reg [7:0] rxhfifo_wstatus;
|
reg [7:0] rxhfifo_wstatus;
|
reg status_crc_error_tog;
|
reg status_crc_error_tog;
|
reg status_fragment_error_tog;
|
reg status_fragment_error_tog;
|
|
reg [13:0] status_good_frame_rx_size;
|
|
reg status_good_frame_rx_tog;
|
reg status_pause_frame_rx_tog;
|
reg status_pause_frame_rx_tog;
|
reg status_rxdfifo_ovflow_tog;
|
reg status_rxdfifo_ovflow_tog;
|
// End of automatics
|
// End of automatics
|
|
|
/*AUTOWIRE*/
|
/*AUTOWIRE*/
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| Line 140... |
Line 146... |
reg [2:0] next_state;
|
reg [2:0] next_state;
|
|
|
reg [13:0] curr_byte_cnt;
|
reg [13:0] curr_byte_cnt;
|
reg [13:0] next_byte_cnt;
|
reg [13:0] next_byte_cnt;
|
|
|
|
reg frame_end_flag;
|
|
reg next_frame_end_flag;
|
|
|
|
reg [2:0] frame_end_bytes;
|
|
reg [2:0] next_frame_end_bytes;
|
|
|
reg fragment_error;
|
reg fragment_error;
|
reg rxd_ovflow_error;
|
reg rxd_ovflow_error;
|
|
|
reg coding_error;
|
reg coding_error;
|
reg next_coding_error;
|
reg next_coding_error;
|
| Line 235... |
Line 247... |
status_fragment_error_tog <= 1'b0;
|
status_fragment_error_tog <= 1'b0;
|
status_rxdfifo_ovflow_tog <= 1'b0;
|
status_rxdfifo_ovflow_tog <= 1'b0;
|
|
|
status_pause_frame_rx_tog <= 1'b0;
|
status_pause_frame_rx_tog <= 1'b0;
|
|
|
|
status_good_frame_rx_tog <= 1'b0;
|
|
status_good_frame_rx_size <= 14'b0;
|
|
|
end
|
end
|
else begin
|
else begin
|
|
|
//---
|
//---
|
// Link status RC layer
|
// Link status RC layer
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| Line 390... |
Line 405... |
|
|
if (good_pause_frame) begin
|
if (good_pause_frame) begin
|
status_pause_frame_rx_tog <= ~status_pause_frame_rx_tog;
|
status_pause_frame_rx_tog <= ~status_pause_frame_rx_tog;
|
end
|
end
|
|
|
|
if (frame_end_flag) begin
|
|
status_good_frame_rx_tog <= ~status_good_frame_rx_tog;
|
|
status_good_frame_rx_size <= curr_byte_cnt + {11'b0, frame_end_bytes};
|
|
end
|
|
|
end
|
end
|
|
|
end
|
end
|
|
|
|
|
| Line 420... |
Line 440... |
|
|
if (reset_xgmii_rx_n == 1'b0) begin
|
if (reset_xgmii_rx_n == 1'b0) begin
|
|
|
curr_state <= SM_IDLE;
|
curr_state <= SM_IDLE;
|
curr_byte_cnt <= 14'b0;
|
curr_byte_cnt <= 14'b0;
|
|
frame_end_flag <= 1'b0;
|
|
frame_end_bytes <= 3'b0;
|
coding_error <= 1'b0;
|
coding_error <= 1'b0;
|
pause_frame <= 1'b0;
|
pause_frame <= 1'b0;
|
|
|
end
|
end
|
else begin
|
else begin
|
|
|
curr_state <= next_state;
|
curr_state <= next_state;
|
curr_byte_cnt <= next_byte_cnt;
|
curr_byte_cnt <= next_byte_cnt;
|
|
frame_end_flag <= next_frame_end_flag;
|
|
frame_end_bytes <= next_frame_end_bytes;
|
coding_error <= next_coding_error;
|
coding_error <= next_coding_error;
|
pause_frame <= next_pause_frame;
|
pause_frame <= next_pause_frame;
|
|
|
end
|
end
|
|
|
| Line 470... |
Line 494... |
next_crc_rx = crc_rx;
|
next_crc_rx = crc_rx;
|
crc_start_8b = 1'b0;
|
crc_start_8b = 1'b0;
|
crc_clear = 1'b0;
|
crc_clear = 1'b0;
|
|
|
next_byte_cnt = curr_byte_cnt;
|
next_byte_cnt = curr_byte_cnt;
|
|
next_frame_end_flag = 1'b0;
|
|
next_frame_end_bytes = 3'b0;
|
|
|
fragment_error = 1'b0;
|
fragment_error = 1'b0;
|
|
|
next_coding_error = coding_error;
|
next_coding_error = coding_error;
|
next_pause_frame = pause_frame;
|
next_pause_frame = pause_frame;
|
| Line 576... |
Line 602... |
//next_byte_cnt = curr_byte_cnt +
|
//next_byte_cnt = curr_byte_cnt +
|
// addmask[0] + addmask[1] + addmask[2] + addmask[3] +
|
// addmask[0] + addmask[1] + addmask[2] + addmask[3] +
|
// addmask[4] + addmask[5] + addmask[6] + addmask[7];
|
// addmask[4] + addmask[5] + addmask[6] + addmask[7];
|
/* verilator lint_on WIDTH */
|
/* verilator lint_on WIDTH */
|
// don't infer a chain of adders
|
// don't infer a chain of adders
|
next_byte_cnt = curr_byte_cnt + {10'b0, bit_cnt8(addmask[7:0])};
|
next_byte_cnt = curr_byte_cnt + {10'b0, bit_cnt8(datamask[7:0])};
|
|
|
|
|
// We will not write to the fifo if all is left
|
// We will not write to the fifo if all is left
|
// are four or less bytes of crc. We also strip off the
|
// are four or less bytes of crc. We also strip off the
|
// crc, which requires looking one cycle ahead
|
// crc, which requires looking one cycle ahead
|
| Line 596... |
Line 622... |
|
|
crc_start_8b = 1'b1;
|
crc_start_8b = 1'b1;
|
next_crc_bytes = 4'd8;
|
next_crc_bytes = 4'd8;
|
next_crc_rx = xgxs_rxd_barrel[31:0];
|
next_crc_rx = xgxs_rxd_barrel[31:0];
|
|
|
|
next_frame_end_flag = 1'b1;
|
|
next_frame_end_bytes = 3'd4;
|
|
|
next_state = SM_IDLE;
|
next_state = SM_IDLE;
|
|
|
end
|
end
|
|
|
if (xgxs_rxd_barrel[`LANE3] == `TERMINATE && xgxs_rxc_barrel[3]) begin
|
if (xgxs_rxd_barrel[`LANE3] == `TERMINATE && xgxs_rxc_barrel[3]) begin
|
| Line 609... |
Line 638... |
|
|
crc_start_8b = 1'b1;
|
crc_start_8b = 1'b1;
|
next_crc_bytes = 4'd7;
|
next_crc_bytes = 4'd7;
|
next_crc_rx = {xgxs_rxd_barrel[23:0], xgxs_rxd_barrel_d1[63:56]};
|
next_crc_rx = {xgxs_rxd_barrel[23:0], xgxs_rxd_barrel_d1[63:56]};
|
|
|
|
next_frame_end_flag = 1'b1;
|
|
next_frame_end_bytes = 3'd3;
|
|
|
next_state = SM_IDLE;
|
next_state = SM_IDLE;
|
|
|
end
|
end
|
|
|
if (xgxs_rxd_barrel[`LANE2] == `TERMINATE && xgxs_rxc_barrel[2]) begin
|
if (xgxs_rxd_barrel[`LANE2] == `TERMINATE && xgxs_rxc_barrel[2]) begin
|
| Line 622... |
Line 654... |
|
|
crc_start_8b = 1'b1;
|
crc_start_8b = 1'b1;
|
next_crc_bytes = 4'd6;
|
next_crc_bytes = 4'd6;
|
next_crc_rx = {xgxs_rxd_barrel[15:0], xgxs_rxd_barrel_d1[63:48]};
|
next_crc_rx = {xgxs_rxd_barrel[15:0], xgxs_rxd_barrel_d1[63:48]};
|
|
|
|
next_frame_end_flag = 1'b1;
|
|
next_frame_end_bytes = 3'd2;
|
|
|
next_state = SM_IDLE;
|
next_state = SM_IDLE;
|
|
|
end
|
end
|
|
|
if (xgxs_rxd_barrel[`LANE1] == `TERMINATE && xgxs_rxc_barrel[1]) begin
|
if (xgxs_rxd_barrel[`LANE1] == `TERMINATE && xgxs_rxc_barrel[1]) begin
|
| Line 635... |
Line 670... |
|
|
crc_start_8b = 1'b1;
|
crc_start_8b = 1'b1;
|
next_crc_bytes = 4'd5;
|
next_crc_bytes = 4'd5;
|
next_crc_rx = {xgxs_rxd_barrel[7:0], xgxs_rxd_barrel_d1[63:40]};
|
next_crc_rx = {xgxs_rxd_barrel[7:0], xgxs_rxd_barrel_d1[63:40]};
|
|
|
|
next_frame_end_flag = 1'b1;
|
|
next_frame_end_bytes = 3'd1;
|
|
|
next_state = SM_IDLE;
|
next_state = SM_IDLE;
|
|
|
end
|
end
|
|
|
if (xgxs_rxd_barrel[`LANE0] == `TERMINATE && xgxs_rxc_barrel[0]) begin
|
if (xgxs_rxd_barrel[`LANE0] == `TERMINATE && xgxs_rxc_barrel[0]) begin
|
| Line 648... |
Line 686... |
|
|
crc_start_8b = 1'b1;
|
crc_start_8b = 1'b1;
|
next_crc_bytes = 4'd4;
|
next_crc_bytes = 4'd4;
|
next_crc_rx = xgxs_rxd_barrel_d1[63:32];
|
next_crc_rx = xgxs_rxd_barrel_d1[63:32];
|
|
|
|
next_frame_end_flag = 1'b1;
|
|
|
next_state = SM_IDLE;
|
next_state = SM_IDLE;
|
|
|
end
|
end
|
|
|
// Look at current cycle for TERMINATE in lanes 5 to 7
|
// Look at current cycle for TERMINATE in lanes 5 to 7
|
| Line 664... |
Line 704... |
|
|
crc_start_8b = 1'b1;
|
crc_start_8b = 1'b1;
|
next_crc_bytes = 4'd3;
|
next_crc_bytes = 4'd3;
|
next_crc_rx = xgxs_rxd_barrel_d1[55:24];
|
next_crc_rx = xgxs_rxd_barrel_d1[55:24];
|
|
|
|
next_frame_end_flag = 1'b1;
|
|
|
next_state = SM_IDLE;
|
next_state = SM_IDLE;
|
|
|
end
|
end
|
|
|
if (xgxs_rxd_barrel_d1[`LANE6] == `TERMINATE &&
|
if (xgxs_rxd_barrel_d1[`LANE6] == `TERMINATE &&
|
| Line 678... |
Line 720... |
|
|
crc_start_8b = 1'b1;
|
crc_start_8b = 1'b1;
|
next_crc_bytes = 4'd2;
|
next_crc_bytes = 4'd2;
|
next_crc_rx = xgxs_rxd_barrel_d1[47:16];
|
next_crc_rx = xgxs_rxd_barrel_d1[47:16];
|
|
|
|
next_frame_end_flag = 1'b1;
|
|
|
next_state = SM_IDLE;
|
next_state = SM_IDLE;
|
|
|
end
|
end
|
|
|
if (xgxs_rxd_barrel_d1[`LANE5] == `TERMINATE &&
|
if (xgxs_rxd_barrel_d1[`LANE5] == `TERMINATE &&
|
| Line 692... |
Line 736... |
|
|
crc_start_8b = 1'b1;
|
crc_start_8b = 1'b1;
|
next_crc_bytes = 4'd1;
|
next_crc_bytes = 4'd1;
|
next_crc_rx = xgxs_rxd_barrel_d1[39:8];
|
next_crc_rx = xgxs_rxd_barrel_d1[39:8];
|
|
|
|
next_frame_end_flag = 1'b1;
|
|
|
next_state = SM_IDLE;
|
next_state = SM_IDLE;
|
|
|
end
|
end
|
end
|
end
|
end
|
end
|
