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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [sync_clk_xgmii_tx.v] - Diff between revs 7 and 12

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Rev 7 Rev 12
Line 38... Line 38...
 
 
`include "defines.v"
`include "defines.v"
 
 
module sync_clk_xgmii_tx(/*AUTOARG*/
module sync_clk_xgmii_tx(/*AUTOARG*/
  // Outputs
  // Outputs
  ctrl_tx_enable_ctx, status_local_fault_ctx,
  ctrl_tx_enable_ctx, status_local_fault_ctx, status_remote_fault_ctx,
  status_remote_fault_ctx,
 
  // Inputs
  // Inputs
  clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable,
  clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable,
  status_local_fault_crx, status_remote_fault_crx
  status_local_fault_crx, status_remote_fault_crx
  );
  );
 
 
Line 59... Line 58...
 
 
output        status_local_fault_ctx;
output        status_local_fault_ctx;
output        status_remote_fault_ctx;
output        status_remote_fault_ctx;
 
 
/*AUTOREG*/
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
 
// End of automatics
 
 
 
/*AUTOWIRE*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
 
// End of automatics
 
 
 
wire  [2:0]             sig_out;
wire  [2:0]             sig_out;
 
 
assign {ctrl_tx_enable_ctx,
assign ctrl_tx_enable_ctx = sig_out[2];
        status_local_fault_ctx,
assign status_local_fault_ctx = sig_out[1];
        status_remote_fault_ctx} = sig_out;
assign status_remote_fault_ctx = sig_out[0];
 
 
meta_sync #(.DWIDTH (3)) meta_sync0 (
meta_sync #(.DWIDTH (3)) meta_sync0 (
                      // Outputs
                      // Outputs
                      .out              (sig_out),
                      .out              (sig_out),
                      // Inputs
                      // Inputs
Line 86... Line 81...
                                          status_remote_fault_crx
                                          status_remote_fault_crx
                                         }));
                                         }));
 
 
endmodule
endmodule
 
 
 
 
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