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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [tx_dequeue.v] - Diff between revs 7 and 10

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Rev 7 Rev 10
Line 111... Line 111... 
reg   [7:0]     xgxs_txc;
 
reg   [7:0]     xgxs_txc;
 
 
 
 
 
reg   [63:0]    next_xgxs_txd;
 
reg   [63:0]    next_xgxs_txd;
 
reg   [7:0]     next_xgxs_txc;
 
reg   [7:0]     next_xgxs_txc;
 
 
 
 
 
reg   [2:0]     curr_state;
 
reg   [2:0]     curr_state_enc;
 
reg   [2:0]     next_state;
 
reg   [2:0]     next_state_enc;
 
 
 
 
 
reg   [0:0]     curr_state_rd;
 
reg   [0:0]     curr_state_pad;
 
reg   [0:0]     next_state_rd;
 
reg   [0:0]     next_state_pad;
 
 
 
 
 
reg             start_on_lane0;
 
reg             start_on_lane0;
 
reg             next_start_on_lane0;
 
reg             next_start_on_lane0;
 
 
 
 
 
reg   [2:0]     ifg_deficit;
 
reg   [2:0]     ifg_deficit;
Line 171... Line 171... 
             SM_TERM      = 3'd4,
 
             SM_TERM      = 3'd4,
 
             SM_TERM_FAIL = 3'd5,
 
             SM_TERM_FAIL = 3'd5,
 
             SM_IFG       = 3'd6;
 
             SM_IFG       = 3'd6;
 
 
 
 
 
parameter [0:0]
 
parameter [0:0]
 
             SM_RD_EQ   = 1'd0,
 
             SM_PAD_EQ    = 1'd0,
 
             SM_RD_PAD  = 1'd1;
 
             SM_PAD_PAD   = 1'd1;
 
 
 
 
 
 
 
 
 
//---
 
//---
 
// RC layer
 
// RC layer
 
 
 
 
Line 223... Line 223... 
 
 
 
 
always @(posedge clk_xgmii_tx or negedge reset_xgmii_tx_n) begin
 
always @(posedge clk_xgmii_tx or negedge reset_xgmii_tx_n) begin
 
 
 
 
 
    if (reset_xgmii_tx_n == 1'b0) begin
 
    if (reset_xgmii_tx_n == 1'b0) begin
 
 
 
 
 
        curr_state <= SM_IDLE;
 
        curr_state_enc <= SM_IDLE;
 
 
 
 
 
        start_on_lane0 <= 1'b1;
 
        start_on_lane0 <= 1'b1;
 
        ifg_deficit <= 3'b0;
 
        ifg_deficit <= 3'b0;
 
        ifg_4b_add <= 1'b0;
 
        ifg_4b_add <= 1'b0;
 
        ifg_8b_add <= 1'b0;
 
        ifg_8b_add <= 1'b0;
Line 248... Line 248... 
        status_txdfifo_udflow_tog <= 1'b0;
 
        status_txdfifo_udflow_tog <= 1'b0;
 
 
 
 
 
    end
 
    end
 
    else begin
 
    else begin
 
 
 
 
 
        curr_state <= next_state;
 
        curr_state_enc <= next_state_enc;
 
 
 
 
 
        start_on_lane0 <= next_start_on_lane0;
 
        start_on_lane0 <= next_start_on_lane0;
 
        ifg_deficit <= next_ifg_deficit;
 
        ifg_deficit <= next_ifg_deficit;
 
        ifg_4b_add <= next_ifg_4b_add;
 
        ifg_4b_add <= next_ifg_4b_add;
 
        ifg_8b_add <= next_ifg_8b_add;
 
        ifg_8b_add <= next_ifg_8b_add;
Line 294... Line 294... 
 
 
 
 
    end
 
    end
 
 
 
 
 
end
 
end
 
 
 
 
 
always @(/*AS*/crc32_tx or ctrl_tx_enable_ctx or curr_state or eop
 
always @(/*AS*/crc32_tx or ctrl_tx_enable_ctx or curr_state_enc or eop
 
         or frame_available or ifg_4b_add or ifg_8b2_add or ifg_8b_add
 
         or frame_available or ifg_4b_add or ifg_8b2_add or ifg_8b_add
 
         or ifg_deficit or start_on_lane0 or status_local_fault_ctx
 
         or ifg_deficit or start_on_lane0 or status_local_fault_ctx
 
         or txhfifo_ralmost_empty or txhfifo_rdata_d1
 
         or txhfifo_ralmost_empty or txhfifo_rdata_d1
 
         or txhfifo_rempty or txhfifo_rstatus) begin
 
         or txhfifo_rempty or txhfifo_rstatus) begin
 
 
 
 
 
    next_state = curr_state;
 
    next_state_enc = curr_state_enc;
 
 
 
 
 
    next_start_on_lane0 = start_on_lane0;
 
    next_start_on_lane0 = start_on_lane0;
 
    next_ifg_deficit = ifg_deficit;
 
    next_ifg_deficit = ifg_deficit;
 
    next_ifg_4b_add = ifg_4b_add;
 
    next_ifg_4b_add = ifg_4b_add;
 
    next_ifg_8b_add = ifg_8b_add;
 
    next_ifg_8b_add = ifg_8b_add;
Line 317... Line 317... 
 
 
 
 
    txhfifo_ren = 1'b0;
 
    txhfifo_ren = 1'b0;
 
 
 
 
 
    next_frame_available = frame_available;
 
    next_frame_available = frame_available;
 
 
 
 
 
    case (curr_state)
 
    case (curr_state_enc)
 
 
 
 
 
        SM_IDLE:
 
        SM_IDLE:
 
          begin
 
          begin
 
 
 
 
 
              // Wait for frame to be available. There should be a least N bytes in the
 
              // Wait for frame to be available. There should be a least N bytes in the
Line 333... Line 333... 
 
 
 
 
              if (ctrl_tx_enable_ctx && frame_available &&
 
              if (ctrl_tx_enable_ctx && frame_available &&
 
                  !status_local_fault_ctx && !status_local_fault_ctx) begin
 
                  !status_local_fault_ctx && !status_local_fault_ctx) begin
 
 
 
 
 
                  txhfifo_ren = 1'b1;
 
                  txhfifo_ren = 1'b1;
 
                  next_state = SM_PREAMBLE;
 
                  next_state_enc = SM_PREAMBLE;
 
 
 
 
 
              end
 
              end
 
              else begin
 
              else begin
 
 
 
 
 
                  next_frame_available = !txhfifo_ralmost_empty;
 
                  next_frame_available = !txhfifo_ralmost_empty;
Line 357... Line 357... 
                 next_xgxs_txd = {`SFD, {6{`PREAMBLE}}, `START};
 
                 next_xgxs_txd = {`SFD, {6{`PREAMBLE}}, `START};
 
                 next_xgxs_txc = 8'h01;
 
                 next_xgxs_txc = 8'h01;
 
 
 
 
 
                 txhfifo_ren = 1'b1;
 
                 txhfifo_ren = 1'b1;
 
 
 
 
 
                 next_state = SM_TX;
 
                 next_state_enc = SM_TX;
 
 
 
 
 
             end
 
             end
 
             else begin
 
             else begin
 
 
 
 
 
                 next_frame_available = 1'b0;
 
                 next_frame_available = 1'b0;
 
                 next_state = SM_IDLE;
 
                 next_state_enc = SM_IDLE;
 
 
 
 
 
             end
 
             end
 
 
 
 
 
 
 
 
 
             // Depending on deficit idle count calculations, add 4 bytes
 
             // Depending on deficit idle count calculations, add 4 bytes
Line 397... Line 397... 
 
 
 
 
              if (txhfifo_rstatus[`TXSTATUS_EOP]) begin
 
              if (txhfifo_rstatus[`TXSTATUS_EOP]) begin
 
 
 
 
 
                  txhfifo_ren = 1'b0;
 
                  txhfifo_ren = 1'b0;
 
                  next_frame_available = !txhfifo_ralmost_empty;
 
                  next_frame_available = !txhfifo_ralmost_empty;
 
                  next_state = SM_EOP;
 
                  next_state_enc = SM_EOP;
 
 
 
 
 
              end
 
              end
 
              else if (txhfifo_rempty || txhfifo_rstatus[`TXSTATUS_SOP]) begin
 
              else if (txhfifo_rempty || txhfifo_rstatus[`TXSTATUS_SOP]) begin
 
 
 
 
 
                  // Failure condition, we did not see EOP and there
 
                  // Failure condition, we did not see EOP and there
 
                  // is no more data in fifo or SOP, force end of packet transmit.
 
                  // is no more data in fifo or SOP, force end of packet transmit.
 
 
 
 
 
                  next_state = SM_TERM_FAIL;
 
                  next_state_enc = SM_TERM_FAIL;
 
 
 
 
 
              end
 
              end
 
 
 
 
 
              next_eop[0] = txhfifo_rstatus[2:0] == 3'd1;
 
              next_eop[0] = txhfifo_rstatus[2:0] == 3'd1;
 
              next_eop[1] = txhfifo_rstatus[2:0] == 3'd2;
 
              next_eop[1] = txhfifo_rstatus[2:0] == 3'd2;
Line 598... Line 598... 
 
 
 
 
                      // Next state depends on number of IFG bytes to be inserted.
 
                      // Next state depends on number of IFG bytes to be inserted.
 
                      // Skip idle state if needed.
 
                      // Skip idle state if needed.
 
 
 
 
 
                      if (next_ifg_8b2_add) begin
 
                      if (next_ifg_8b2_add) begin
 
                          next_state = SM_IFG;
 
                          next_state_enc = SM_IFG;
 
                      end
 
                      end
 
                      else if (next_ifg_8b_add) begin
 
                      else if (next_ifg_8b_add) begin
 
                          next_state = SM_IDLE;
 
                          next_state_enc = SM_IDLE;
 
                      end
 
                      end
 
                      else begin
 
                      else begin
 
                          txhfifo_ren = 1'b1;
 
                          txhfifo_ren = 1'b1;
 
                          next_state = SM_PREAMBLE;
 
                          next_state_enc = SM_PREAMBLE;
 
                      end
 
                      end
 
 
 
 
 
                  end
 
                  end
 
                  else begin
 
                  else begin
 
                      next_state = SM_IFG;
 
                      next_state_enc = SM_IFG;
 
                  end
 
                  end
 
              end
 
              end
 
 
 
 
 
              if (|eop[7:3]) begin
 
              if (|eop[7:3]) begin
 
                  next_state = SM_TERM;
 
                  next_state_enc = SM_TERM;
 
              end
 
              end
 
 
 
 
 
          end
 
          end
 
 
 
 
 
        SM_TERM:
 
        SM_TERM:
Line 656... Line 656... 
              // Next state depends on number of IFG bytes to be inserted.
 
              // Next state depends on number of IFG bytes to be inserted.
 
              // Skip idle state if needed.
 
              // Skip idle state if needed.
 
 
 
 
 
              if (frame_available && !ifg_8b_add) begin
 
              if (frame_available && !ifg_8b_add) begin
 
                  txhfifo_ren = 1'b1;
 
                  txhfifo_ren = 1'b1;
 
                  next_state = SM_PREAMBLE;
 
                  next_state_enc = SM_PREAMBLE;
 
              end
 
              end
 
              else if (frame_available) begin
 
              else if (frame_available) begin
 
                  next_state = SM_IDLE;
 
                  next_state_enc = SM_IDLE;
 
              end
 
              end
 
              else begin
 
              else begin
 
                  next_state = SM_IFG;
 
                  next_state_enc = SM_IFG;
 
              end
 
              end
 
 
 
 
 
          end
 
          end
 
 
 
 
 
        SM_TERM_FAIL:
 
        SM_TERM_FAIL:
 
          begin
 
          begin
 
 
 
 
 
              next_xgxs_txd = {{7{`IDLE}}, `TERMINATE};
 
              next_xgxs_txd = {{7{`IDLE}}, `TERMINATE};
 
              next_xgxs_txc = 8'b11111111;
 
              next_xgxs_txc = 8'b11111111;
 
              next_state = SM_IFG;
 
              next_state_enc = SM_IFG;
 
 
 
 
 
          end
 
          end
 
 
 
 
 
        SM_IFG:
 
        SM_IFG:
 
          begin
 
          begin
 
 
 
 
 
              next_state = SM_IDLE;
 
              next_state_enc = SM_IDLE;
 
 
 
 
 
          end
 
          end
 
 
 
 
 
        default:
 
        default:
 
          begin
 
          begin
 
              next_state = SM_IDLE;
 
              next_state_enc = SM_IDLE;
 
          end
 
          end
 
 
 
 
 
    endcase
 
    endcase
 
 
 
 
 
end
 
end
Line 704... Line 704... 
        crc_data = crc32_d64;
 
        crc_data = crc32_d64;
 
    end
 
    end
 
 
 
 
 
end
 
end
 
 
 
 
 
always @(/*AS*/byte_cnt or curr_state_rd or txdfifo_rdata
 
always @(/*AS*/byte_cnt or curr_state_pad or txdfifo_rdata
 
         or txdfifo_rempty or txdfifo_ren_d1 or txdfifo_rstatus
 
         or txdfifo_rempty or txdfifo_ren_d1 or txdfifo_rstatus
 
         or txhfifo_walmost_full) begin
 
         or txhfifo_walmost_full) begin
 
 
 
 
 
    next_state_rd = curr_state_rd;
 
    next_state_pad = curr_state_pad;
 
 
 
 
 
    next_txhfifo_wdata = txdfifo_rdata;
 
    next_txhfifo_wdata = txdfifo_rdata;
 
    next_txhfifo_wstatus = txdfifo_rstatus;
 
    next_txhfifo_wstatus = txdfifo_rstatus;
 
 
 
 
 
    txdfifo_ren = 1'b0;
 
    txdfifo_ren = 1'b0;
 
    next_txhfifo_wen = 1'b0;
 
    next_txhfifo_wen = 1'b0;
 
 
 
 
 
    case (curr_state_rd)
 
    case (curr_state_pad)
 
 
 
 
 
      SM_RD_EQ: begin
 
      SM_PAD_EQ: begin
 
 
 
 
 
 
 
 
 
          //---
 
          //---
 
          // If room availabe in hoding fifo and data available in
 
          // If room availabe in hoding fifo and data available in
 
          // data fifo, transfer data words. If transmit state machine
 
          // data fifo, transfer data words. If transmit state machine
Line 748... Line 748... 
 
 
 
 
                  if (byte_cnt < 14'd56) begin
 
                  if (byte_cnt < 14'd56) begin
 
 
 
 
 
                      next_txhfifo_wstatus = `TXSTATUS_NONE;
 
                      next_txhfifo_wstatus = `TXSTATUS_NONE;
 
                      txdfifo_ren = 1'b0;
 
                      txdfifo_ren = 1'b0;
 
                      next_state_rd = SM_RD_PAD;
 
                      next_state_pad = SM_PAD_PAD;
 
 
 
 
 
                  end
 
                  end
 
                  else if (byte_cnt == 14'd56 &&
 
                  else if (byte_cnt == 14'd56 &&
 
                           (txdfifo_rstatus[2:0] == 3'd1 ||
 
                           (txdfifo_rstatus[2:0] == 3'd1 ||
 
                            txdfifo_rstatus[2:0] == 3'd2 ||
 
                            txdfifo_rstatus[2:0] == 3'd2 ||
Line 785... Line 785... 
 
 
 
 
          end
 
          end
 
 
 
 
 
      end
 
      end
 
 
 
 
 
      SM_RD_PAD: begin
 
      SM_PAD_PAD: begin
 
 
 
 
 
          //---
 
          //---
 
          // Pad packet to 64 bytes by writting zeros to holding fifo.
 
          // Pad packet to 64 bytes by writting zeros to holding fifo.
 
 
 
 
 
          if (!txhfifo_walmost_full) begin
 
          if (!txhfifo_walmost_full) begin
Line 805... Line 805... 
                  // be inserted by dequeue engine.
 
                  // be inserted by dequeue engine.
 
 
 
 
 
                  next_txhfifo_wstatus[`TXSTATUS_EOP] = 1'b1;
 
                  next_txhfifo_wstatus[`TXSTATUS_EOP] = 1'b1;
 
                  next_txhfifo_wstatus[2:0] = 3'd4;
 
                  next_txhfifo_wstatus[2:0] = 3'd4;
 
 
 
 
 
                  next_state_rd = SM_RD_EQ;
 
                  next_state_pad = SM_PAD_EQ;
 
 
 
 
 
              end
 
              end
 
 
 
 
 
          end
 
          end
 
 
 
 
 
      end
 
      end
 
 
 
 
 
      default:
 
      default:
 
        begin
 
        begin
 
            next_state_rd = SM_RD_EQ;
 
            next_state_pad = SM_PAD_EQ;
 
        end
 
        end
 
 
 
 
 
    endcase
 
    endcase
 
 
 
 
 
end
 
end
Line 827... Line 827... 
 
 
 
 
always @(posedge clk_xgmii_tx or negedge reset_xgmii_tx_n) begin
 
always @(posedge clk_xgmii_tx or negedge reset_xgmii_tx_n) begin
 
 
 
 
 
    if (reset_xgmii_tx_n == 1'b0) begin
 
    if (reset_xgmii_tx_n == 1'b0) begin
 
 
 
 
 
        curr_state_rd <= SM_RD_EQ;
 
        curr_state_pad <= SM_PAD_EQ;
 
 
 
 
 
        txdfifo_ren_d1 <= 1'b0;
 
        txdfifo_ren_d1 <= 1'b0;
 
 
 
 
 
        txhfifo_wdata <= 64'b0;
 
        txhfifo_wdata <= 64'b0;
 
        txhfifo_wstatus <= 8'b0;
 
        txhfifo_wstatus <= 8'b0;
Line 844... Line 844... 
        shift_crc_cnt <= 4'b0;
 
        shift_crc_cnt <= 4'b0;
 
 
 
 
 
    end
 
    end
 
    else begin
 
    else begin
 
 
 
 
 
        curr_state_rd <= next_state_rd;
 
        curr_state_pad <= next_state_pad;
 
 
 
 
 
        txdfifo_ren_d1 <= txdfifo_ren;
 
        txdfifo_ren_d1 <= txdfifo_ren;
 
 
 
 
 
        txhfifo_wdata <= next_txhfifo_wdata;
 
        txhfifo_wdata <= next_txhfifo_wdata;
 
        txhfifo_wstatus <= next_txhfifo_wstatus;
 
        txhfifo_wstatus <= next_txhfifo_wstatus;

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