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[/] [xge_mac/] [trunk/] [rtl/] [verilog/] [tx_dequeue.v] - Diff between revs 10 and 12

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Rev 10 Rev 12
Line 101... Line 101...
reg [7:0]               xgmii_txc;
reg [7:0]               xgmii_txc;
reg [63:0]              xgmii_txd;
reg [63:0]              xgmii_txd;
// End of automatics
// End of automatics
 
 
/*AUTOWIRE*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
 
// End of automatics
 
 
 
 
 
reg   [63:0]    xgxs_txd;
reg   [63:0]    xgxs_txd;
reg   [7:0]     xgxs_txc;
reg   [7:0]     xgxs_txc;
 
 

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